Displaying 7 results from an estimated 7 matches for "vrp_2048".
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vr_2048
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
You are right. But when i defined my instruction as follows:
def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst,
$src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32
VRP_2048:$src2)))]>, VEX_4V;
I get opcode conflicts? Then what to do?
On Tue, Sep 5, 2017 at 3:51 AM, Craig Topper <crai...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
...at gmail.com> wrote:
> Leave TA. Put both.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> You are right. But when i defined my instruction as follows:
>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V;
>>
>> I get opcode conflicts? Then what to do?
>>
&...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
...>>> ~Craig
>>>
>>> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>> wrote:
>>>
>>>> You are right. But when i defined my instruction as follows:
>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V;
>>>>
>>>> I get opcod...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...;>>> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>>>> wrote:
>>>>>
>>>>>> You are right. But when i defined my instruction as follows:
>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V;
>>>>>&...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Thank You.
My add instruction has TA as follows:
def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst,
$src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32
VRP_2048:$src2)))]>, TA;
so i defined;
bool HasTA = TSFlags & X86II::TA; in x86MCCodeEmitter.cpp
then used this cond...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...7 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> You are right. But when i defined my instruction as follows:
>>>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Hello,
I am trying to emit binary for my implemented vector instructions. Although
yet i havent done any change or addition in MC framework, For vector load
instruction there are no error coming. But for vector add
instruction is something like this;
> %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>,
%R_0_REG2048b_0<kill>
I am getting the following error:
Unknown