Displaying 4 results from an estimated 4 matches for "vreg99".
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2017 Jun 15
2
LLC does not do proper copy propagation (or copy coalescing)
Hello.
Could you please tell me how can I optimize with the back end (llc) the following
piece of assembly code generated by llc:
// NOTE: my processor accepts loops in the form of REPEAT(num_times)..END_REPEAT
R0 = ...
REPEAT(256)
R5 = R0; // basically unnecessary reg. copy
REPEAT(256)
R10 = LS[R4];
R2 = LS[R5];
R4 =
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...his case, but I don't think it can properly handle this in general. For example:
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
%vreg99<def> = PHI %vreg13, <BB#1>, %vreg2, <BB#0>
%vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
%vreg13<def> = BDNZ8 %vreg13, <BB#1>; CTRRC8:%vreg13
B <BB#2>
Successors according to CFG: BB#2 BB#1
Since it is impossible to copy %vreg1...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
Hello again,
I am trying to implement an optimization pass for PowerPC such that
simple loops use the special "counter register" (CTR) to track the
induction variable. This is helpful because, in addition to reducing
register pressure, there is a combined decrement-compare-and-branch
instruction BZND (there are also other related instructions).
I started this process by converting the
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...think it can properly handle this in general. For example:
>
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
> <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 %vreg99<def> = PHI %vreg13,
> <BB#1>, %vreg2, <BB#0> %vreg13<def> = COPY %vreg12<kill>;
> CTRRC8:%vreg13,%vreg12 %vreg13<def> = BDNZ8 %vreg13, <BB#1>;
> CTRRC8:%vreg13 B <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> Since i...