Displaying 20 results from an estimated 52 matches for "vreg9".
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2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...::SlotIndex): Assertion `validator.rangesOk() && "moveAllOperandsFrom
broke liveness."' failed.
The code being scheduled (function "push") is trivial:
# Machine code for function push: Post SSA
Function Live Outs: %R0
0B BB#0: derived from LLVM BB %entry
16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LD...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...&& "moveAllOperandsFrom
> broke liveness."' failed.
>
> The code being scheduled (function "push") is trivial:
>
> # Machine code for function push: Post SSA
> Function Live Outs: %R0
>
> 0B BB#0: derived from LLVM BB %entry
> 16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...introduced:
>
> # *** IR Dump After Eliminate PHI nodes for register allocation ***:
> # Machine code for function push: Post SSA
> Function Live Outs: %R0
>
> BB#0: derived from LLVM BB %entry
> %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
> %vreg9<def> = COPY %vreg4<kill>; IntRegs:%vreg9,%vreg4
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg0<def> = COPY %vreg9<kill>; IntRegs:%vreg0,%vreg9
> %vreg1<de...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value.
%vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg2,%vreg0
By the time it has gotten to the scheduler, it became this:
BB#0: derived from LLVM BB %entry
%vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<<<<<<&...
2017 Nov 30
2
TwoAddressInstructionPass bug?
...BMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
+ let hasSideEffects = 0 in
+ def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
The input to TwoAddress is:
BB#0: derived from LLVM BB %0
Live Ins: %r2l
%vreg0<def> = COPY %r2l<kill>; GR32Bit:%vreg0
%vreg9<def,tied1> = NIFMux %vreg0<tied0>, 14,
%cc<imp-def,dead>; GRX32Bit:%vreg9 GR32Bit:%vreg0
%vreg4<def,tied1> = NIFMux %vreg0<tied0>, 254,
%cc<imp-def,dead>; GRX32Bit:%vreg4 GR32Bit:%vreg0
%vreg2<def> = COPY %vreg0<kill>; GR32Bit:%vre...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...t;<<<<<<<<< Use of that dummy value.
> %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0
>
>
> By the time it has gotten to the scheduler, it became this:
>
> BB#0: derived from LLVM BB %entry
> %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 <<<<<&...
2012 Jan 19
4
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...-class-join" to be sure the resulting code is ok?
I have several cases where cross class joins are carried out that makes
the code turn out illegal, because the "new" register class is not
allowed in all instructions where it is now used.
For example, by joining %vreg4, %vreg7 and %vreg9 the following code
%vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
%vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
%vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
is turned into
%vreg17<def> = load %vreg4:lo16&...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...2:%vreg6,%vreg4,%vreg5
%vreg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2
%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
%vreg10<def> = IMPLICIT_DEF; R600_Reg128:%vreg10
%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6
RESERVE_REG 1
RESERVE_REG 2
%vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8
%vreg13<...
2013 Apr 24
1
[LLVMdev] use of ARM GPRPair register class
...PRPair sub-registers
can be used by instructions that do not return 64 bit value?
Example:
This is a simple example of machine instructions I caused to be generated. I
forced the LDRi12 instructions to use a GPRPair sub-register.
The copy into %vreg4 asserts because of the two definitions of vreg9,
coming from vreg9:gsub_0 and vreg9:gsub_1.
%vreg1<def> = COPY %R1; GPR:%vreg1
%vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2
%vreg3<def> = ADDrsi %vreg2<kill>, %vreg1, 18, pred:14, pred:%noreg,
opt:%noreg; GPR:%vreg3,%vreg2,%vreg1
%...
2012 Jan 19
0
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...he resulting code is ok?
No.
> I have several cases where cross class joins are carried out that makes
> the code turn out illegal, because the "new" register class is not
> allowed in all instructions where it is now used.
>
> For example, by joining %vreg4, %vreg7 and %vreg9 the following code
>
> %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4
> %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7
> %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9
>
> is turned into
>
> %v...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...I DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
# preds left : 0
# succs left : 3
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
Successors:
val SU(3): Latency=1
val SU(2): Latency=1
antiSU(2): Latency=0
SU...
2017 Nov 30
0
TwoAddressInstructionPass bug?
...X32>;
> + let hasSideEffects = 0 in
> + def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
>
> The input to TwoAddress is:
>
> BB#0: derived from LLVM BB %0
> Live Ins: %r2l
> %vreg0<def> = COPY %r2l<kill>; GR32Bit:%vreg0
> %vreg9<def,tied1> = NIFMux %vreg0<tied0>, 14, %cc<imp-def,dead>; GRX32Bit:%vreg9 GR32Bit:%vreg0
> %vreg4<def,tied1> = NIFMux %vreg0<tied0>, 254, %cc<imp-def,dead>; GRX32Bit:%vreg4 GR32Bit:%vreg0
> %vreg2<def> = COPY %vreg0<kill>; GR32Bi...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...statement
if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
should guarantee? From it there must be more than one definition in MRI.def
for that reg for it to work...
To connect it to the original example... When parsing (BU order) this
instruction:
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
The %vreg10<def> never inserted to VRegDefs, so with next instruction:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
Anti dep on %vreg10 is never created.
Thanks.
Sergei
--
Qualcomm Innovation Center, Inc. is a member...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...Right after the dead vreg is introduced:
# *** IR Dump After Eliminate PHI nodes for register allocation ***:
# Machine code for function push: Post SSA
Function Live Outs: %R0
BB#0: derived from LLVM BB %entry
%vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
%vreg9<def> = COPY %vreg4<kill>; IntRegs:%vreg9,%vreg4
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
%vreg0<def> = COPY %vreg9<kill>; IntRegs:%vreg0,%vreg9
%vreg1<def> = COPY %vreg10<...
2014 Oct 27
4
[LLVMdev] Problem in X86 backend
Hi,
I'm having some trouble wirting an instruction in the X86 backend.
I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend.
Everything works fine, except for one instruction that I can't find how to write.
I want to add this instruction in one of my machine basic block: mov [rdi], 0
How can I achieve that with the LLVM api? I tried several
2017 Aug 02
3
[InstCombine] Simplification sometimes only transforms but doesn't simplify instruction, causing side effect in other pass
...y the transformation, however currently live
Interval information is not ready in both places.
* The pattern matching looks quite ad hoc on machine IR. I need to
figure out we can replace %vreg0 in "AND32ri8 %vreg0<tied0>, 31" with
%vreg1 by looking at the copy chain starting from %vreg9<def> = COPY
%vreg0 to %vreg1<def> = MOVZX32rr8 %vreg9 first, and at the same time,
after replacing vreg0 with %vreg1, vreg0 becomes dead at the other
AND32ri and we can save an instruction there. In addition, replace
%vreg0 with %vreg1 may increase an extra move before "AND32ri8
%v...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...def_end())
>
> should guarantee? From it there must be more than one definition in MRI.def
> for that reg for it to work...
>
>
>
>
> To connect it to the original example... When parsing (BU order) this
> instruction:
>
> SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
>
> The %vreg10<def> never inserted to VRegDefs, so with next instruction:
>
> SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
>
> Anti dep on %vreg10 is never created.
Thanks for the detailed explanatio...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...tency.
It seems the issue is with load clustering. I restrict load clustering
to 4 at a time, but when I look at the debug output, the loads are
always being scheduled based on the fact that that are clustered. e.g.
Pick Top CLUSTER
Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9
I have a feeling there is something wrong with my machine model in the
R600 backend, but I've experimented with a few variations of it and have
been unable to solve this problem. Does anyone have any idea what I
might be doing wrong...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
.... I restrict load clustering
> > to 4 at a time, but when I look at the debug output, the loads are
> > always being scheduled based on the fact that that are clustered. e.g.
> >
> > Pick Top CLUSTER
> > Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9
>
> Well, only 4 loads in a sequence should have the “cluster” edges. You should be able to see that when the DAG is printed before scheduling.
>
There are 4 consecutive 'Pick Top CLUSTER' then a 'Pick Top WEAK'...