search for: vreg79

...consecutive registers. Operand 1 has no particular constraint. It has no output register. So we have something like MPQD R_n, R_x, R_n+1. I have derived from PBQPBuilder to add the MPQD constraint. It happens sometimes that the code for register allocation looks like this : ... MPQD %vreg80, %vreg79, %vreg80; GR16:%vreg80,%vreg79 ... Operands 0 & 2 have been coalesced and I can no longer set the constraint. I tried to add a pass right before register allocation, to catch those case and insert a copy for operand 2, but the copy gets coalesced away. What would be the appropriate way to...

...has no particular constraint. It has no output register. So we have something like MPQD R_n, R_x, R_n+1. > > I have derived from PBQPBuilder to add the MPQD constraint. > > It happens sometimes that the code for register allocation looks like this : > ... > MPQD %vreg80, %vreg79, %vreg80; GR16:%vreg80,%vreg79 > ... > Operands 0 & 2 have been coalesced and I can no longer set the constraint. > > I tried to add a pass right before register allocation, to catch those case and insert a copy for operand 2, but the copy gets coalesced away. > > What...

...t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 t20: i32 = AssertZext t18, ValueType:ch:i1 t23: i1 = setcc...

...eg507 >> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6, t9 >> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 >> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 >> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 >> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 >> t20: i32 = AssertZext t18, Value...

...rticular constraint. It has no output register. > So we have something like MPQD R_n, R_x, R_n+1. > > I have derived from PBQPBuilder to add the MPQD constraint. > > It happens sometimes that the code for register allocation looks > like this : > ... > MPQD %vreg80, %vreg79, %vreg80; GR16:%vreg80,%vreg79 > ... > Operands 0 & 2 have been coalesced and I can no longer set the > constraint. > > I tried to add a pass right before register allocation, to catch > those case and insert a copy for operand 2, but the copy gets > coalesced away...