Displaying 2 results from an estimated 2 matches for "vreg72".
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vreg2
2013 Feb 12
0
[LLVMdev] Emulating an infinite register file in the backend
...that you used an easy "trick" for defining an infinite
> register file in the backend.
>
The original PTX back-end just didn't perform register allocation. All
registers emitted in the assembly were virtual registers, mapped to a
consecutive range. E.g., %vreg7, %vreg13, and %vreg72 might be emitted as
%r0, %r1, %r2. Just before machine code emission, we scanned the function
to determine this range. Unfortunately, during the switch to the NVPTX
back-end, some changes were made in LLVM that prevented this from working
in some cases. Basically, some post-regalloc passes were...
2013 Feb 11
2
[LLVMdev] Emulating an infinite register file in the backend
Hi Justin and all,
you've mentioned that you used an easy "trick" for defining an
infinite register file in the backend.
Does this involve defining a single dummy register, and then adding
this dummy reg to each register class? Is anything more needed? I
refer to the RegisterInfo.td file, as e.g:
llvm-3.0.src/lib/Target/PTX/PTXRegisterInfo.td
I'm (just starting)