Displaying 9 results from an estimated 9 matches for "vreg68".
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2017 Feb 02
3
Register allocator behaves differently when compiling with and without -g
...x for each instruction. As an example, without -g
a snippet of a basic block looks like this:
32B %vreg29<def> = LDImm 1; REG1:%vreg29
36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
44B %vreg68<def> = LDImm 12345; REG1:%vreg68
64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143
72B %vreg78<def> = LDImm 32; REG1:%vreg78
But when I specify -g, this becomes:
32B %vreg29<def> = LDImm 1; REG1:%vreg29 dbg:path/to/source:9:34 @[
path/...
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
...s an example, without -g a snippet of a basic block looks like this:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29
> 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
> 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
> 44B %vreg68<def> = LDImm 12345; REG1:%vreg68
> 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143
> 72B %vreg78<def> = LDImm 32; REG1:%vreg78
>
> But when I specify -g, this becomes:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29 db...
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
...s an example, without -g a snippet of a basic block looks like this:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29
> 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
> 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
> 44B %vreg68<def> = LDImm 12345; REG1:%vreg68
> 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143
> 72B %vreg78<def> = LDImm 32; REG1:%vreg78
>
> But when I specify -g, this becomes:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29 db...
2014 Sep 05
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
...15]
0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] [ID=23]
0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738 [ORD=2] [ID=20]
0x7f91b99acc60: i64,ch = CopyFromReg 0x7f91b8d52820, 0x7f91b99a3a10 [ORD=2] [ID=16]
0x7f91b99a3a10: i64 = Register %vreg68 [ID=1]
0x7f91b99ace70: i64 = Constant<0> [ID=3]
In function: isamax0
clang: error: clang frontend command failed with exit code 70 (use -v to see invocation)
clang version 3.6.0 (215249)
Target: x86_64-apple-darwin14.0.0
For some reason, I cannot reproduce the problem with the test case...
2014 Sep 06
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
...1b99ab840 [ORD=2]
>> [ID=23]
>> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738
>> [ORD=2] [ID=20]
>> 0x7f91b99acc60: i64,ch = CopyFromReg 0x7f91b8d52820,
>> 0x7f91b99a3a10 [ORD=2] [ID=16]
>> 0x7f91b99a3a10: i64 = Register %vreg68 [ID=1]
>> 0x7f91b99ace70: i64 = Constant<0> [ID=3]
>> In function: isamax0
>> clang: error: clang frontend command failed with exit code 70 (use -v to
>> see invocation)
>> clang version 3.6.0 (215249)
>> Target: x86_64-apple-darwin14.0.0
>>
>&...
2014 Sep 08
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
...64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] [ID=23]
>> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738 [ORD=2] [ID=20]
>> 0x7f91b99acc60: i64,ch = CopyFromReg 0x7f91b8d52820, 0x7f91b99a3a10 [ORD=2] [ID=16]
>> 0x7f91b99a3a10: i64 = Register %vreg68 [ID=1]
>> 0x7f91b99ace70: i64 = Constant<0> [ID=3]
>> In function: isamax0
>> clang: error: clang frontend command failed with exit code 70 (use -v to see invocation)
>> clang version 3.6.0 (215249)
>> Target: x86_64-apple-darwin14.0.0
>>
>> For...
2014 Sep 09
5
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
...t;> [ID=23]
>>> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738
>>> [ORD=2] [ID=20]
>>> 0x7f91b99acc60: i64,ch = CopyFromReg 0x7f91b8d52820,
>>> 0x7f91b99a3a10 [ORD=2] [ID=16]
>>> 0x7f91b99a3a10: i64 = Register %vreg68 [ID=1]
>>> 0x7f91b99ace70: i64 = Constant<0> [ID=3]
>>> In function: isamax0
>>> clang: error: clang frontend command failed with exit code 70 (use -v to
>>> see invocation)
>>> clang version 3.6.0 (215249)
>>> Target: x86_64-apple-dar...
2014 Sep 05
3
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
On Fri, Sep 5, 2014 at 9:32 AM, Robert Lougher <rob.lougher at gmail.com>
wrote:
> Unfortunately, another team, while doing internal testing has seen the
> new path generating illegal insertps masks. A sample here:
>
> vinsertps $256, %xmm0, %xmm13, %xmm4 # xmm4 = xmm0[0],xmm13[1,2,3]
> vinsertps $256, %xmm1, %xmm0, %xmm6 # xmm6 = xmm1[0],xmm0[1,2,3]
>
2014 Sep 09
1
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
...0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738
>>>>> [ORD=2] [ID=20]
>>>>> 0x7f91b99acc60: i64,ch = CopyFromReg 0x7f91b8d52820,
>>>>> 0x7f91b99a3a10 [ORD=2] [ID=16]
>>>>> 0x7f91b99a3a10: i64 = Register %vreg68 [ID=1]
>>>>> 0x7f91b99ace70: i64 = Constant<0> [ID=3]
>>>>> In function: isamax0
>>>>> clang: error: clang frontend command failed with exit code 70 (use -v to
>>>>> see invocation)
>>>>> clang version 3.6.0 (215249...