search for: vreg62

...and the uses appear before the definition, then the copies should be coalesced away. In the examples that you show below, it all depends in which iteration each instruction is scheduled and/or the order in which the instructions are scheduled. %vreg73<def> = PHI %vreg59, <BB#5>, %vreg62, <BB#6>; %vreg61<def> = INSN1 %vreg1, %vreg73; %vreg62<def> = INSN2 %vreg73, %vreg5; %vreg64<def> = INSN1 %vreg2, %vreg73; For some reason, the instruction defining vreg64 was scheduled after the instruction defining vreg62, which causes the copy to be generated...

..., the assignment (2) basically reads an undefined register. A scenario like this happens in real life. Look at vreg304 below: BB#2: derived from LLVM BB %if.end Predecessors according to CFG: BB#1 %vreg61<def> = LDrih_indexed %vreg56, 3134; IntRegs:%vreg61,%vreg56 %vreg62<def> = LDriuh_indexed %vreg56, 680; IntRegs:%vreg62,%vreg56 %R1<def> = TFRI 1431655766 ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-use>, %R30<imp-use>, %R29<imp-use> %vreg304:subreg_loreg<def,read-undef> = AD...

Hi - I replied to the original sender only by mistake. Sorry about that. When we started working on the pipeliner, and added it before the scheduler, we also were concerned that the scheduler or other passes would undo the work of the pipeliner. The initial thought was that we would add information (using metadata or some other way like you've suggested) to the basic block to tell the

Hi, I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp. First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes. Why not put