Displaying 3 results from an estimated 3 matches for "vreg57".
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vreg27
2012 Jan 05
0
[LLVMdev] Spilling of partly (un)defined registers
...efore Linear Scan Register Allocator ***:
# Machine code for function accumconv:
Function Live Ins: %a0_gh in %vreg0, %a1_gh in %vreg1
BB#0: derived from LLVM BB %0
Live Ins: %a0_gh %a1_gh
%vreg1<def> = COPY %a1_gh; aNgh_0_7:%vreg1
[...]
%vreg56<def> = mv_any16 0; aNl_0_7:%vreg56
%vreg57<def> = REG_SEQUENCE %vreg1, hi24, %vreg56, lo16;
aN40_0_7:%vreg57 aNgh_0_7:%vreg1 aNl_0_7:%vreg56
So the in-argument in a1_gh is saved in vreg1, and used later in a
REG_SEQUENCE instruction to write a full register, vreg57.
After the REG_SEQUENCE has been eliminated we instead get
16 %vre...
2012 Jul 04
2
[LLVMdev] Assertion in PHIElimination.cpp
...ADJCALLSTACKDOWN 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use>
CALLi <ga:@clock_get_ticks>, <regmask>, %SP<imp-use>, %SP<imp-def>, %A<imp-def>, ...
ADJCALLSTACKUP 0, 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use>
%vreg57<def> = COPY %A<kill>; GR16:%vreg57
%vreg58<def> = SUB16rr %vreg57, %vreg18<kill>, %EX<imp-def>; GR16:%vreg58,%vreg57 GEXR16:%vreg18
%vreg59<def> = ADD16rm %vreg58<kill>, <fi#1>, 16, %EX<imp-def>; mem:LD1[%sunkaddr21](align=8)(tba...
2017 Feb 21
2
Error at Pre-regalloc Machine LICM: "getVRegDef assumes a single definition or no definition"' failed.
...ef> = VLOAD_D 0; MSA128D:%vreg51
Hoisting %vreg51<def> = VLOAD_D 0; MSA128D:%vreg51
from BB#4 to BB#3
Can't remat / high reg-pressure: %vreg54<def> = COPY %vreg50; BoolMask:%vreg54
MSA128D:%vreg50 dbg:IfVectorize.c:37:16
Can't remat / high reg-pressure: %vreg57<def> = COPY %vreg50; BoolMask:%vreg57
MSA128D:%vreg50 dbg:IfVectorize.c:37:16
Entering BB#15
Hoisting %vreg66<def> = LD_imm64 4294967296; GPR:%vreg66
from BB#15 to BB#6
Entering BB#12
Hoist non-reg-pressure: %vreg83<def> = VLOAD_D 3; MSA128D:%vreg83 dbg:...