search for: vreg27

...; = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 register: %vreg26 +[224r,336r:0) 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 register: %vreg27 +[256r,304r:0) 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 register: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 2...

...00_Reg128:%vreg26,%vreg23 > register: %vreg26 +[224r,336r:0) > 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 > R600_TReg32:%vreg16 > register: %vreg26 replace range with [224r,240r:1) RESULT: > [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r > 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 > register: %vreg27 +[256r,304r:0) > 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 > R600_Reg32:%vreg25 > register: %vreg27 replace range with [256r,272r:1) RESULT: > [256r,272r:1)[272...

...%vreg41<kill>; R600_Reg32:%vreg41 > 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 R600_Reg128:%vreg6 > 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 > > And after the pass : > > //Before Loop > ...Some COPYs... > 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 > 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 > 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 > 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 > > //LOOP CONDITION > 5...

...128:%vreg6 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 R600_Reg128:%vreg6 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 And after the pass : //Before Loop ...Some COPYs... 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 //LOOP CONDITION 512B%vreg30<def> = SETGT...

...%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 %vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 %vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 %vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 %vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 %vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 %vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 %vreg3:sel_w&lt...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...f> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 > %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 > %vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 > %vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 > %vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 > %vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 > %vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > %vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27...

...reg10<def> = CMPEQI %vreg9<kill>, 0, pred:%noreg; PredRegs:%vreg10 IntRegs:%vreg9 dbg:../src/getbits.c:46:1 96B JUMP <BB#2>, pred:%vreg10<kill>; PredRegs:%vreg10 Successors according to CFG: BB#2(12) BB#1(20) 112B BB#1: Predecessors according to CFG: BB#0 128B %vreg27<def> = MOV32ri -1, pred:%noreg; IntRegs:%vreg27 160B JUMP <BB#5>, pred:%noreg Successors according to CFG: BB#5 176B BB#2: derived from LLVM BB %while.cond.preheader Predecessors according to CFG: BB#0 192B %vreg27<def> = MOV32ri 0, pred:%noreg; IntRegs:%vreg27 208B...

...owing live ranges when I start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26...

...)[352r,416r:5)... > R3 = [0B,48r:0)[368r,416r:5)... > R4 = [0B,32r:0)[384r,416r:4)... > R5 = [0B,32r:0)[400r,416r:4)... > > I schedule the following instruction (48B): > > 0B BB#0: derived from LLVM BB %entry > Live Ins: %R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B...

...start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY...

On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote: > The code in collectRanges() does: > > // Collect ranges for register units. These live ranges are computed on > // demand, so just skip any that haven't been computed yet. > if (TargetRegisterInfo::isPhysicalRegister(Reg)) { > for (MCRegUnitIterator Units(Reg,

...; > R2 = [0B,48r:0)[352r,416r:5)... > R3 = [0B,48r:0)[368r,416r:5)... > R4 = [0B,32r:0)[384r,416r:4)... > R5 = [0B,32r:0)[400r,416r:4)... > > I schedule the following instruction (48B): > > 0B BB#0: derived from LLVM BB %entry > Live Ins: %R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<...

The code in collectRanges() does: // Collect ranges for register units. These live ranges are computed on // demand, so just skip any that haven't been computed yet. if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))

...start scheduling a region: R2 = [0B,48r:0)[352r,416r:5)... R3 = [0B,48r:0)[368r,416r:5)... R4 = [0B,32r:0)[384r,416r:4)... R5 = [0B,32r:0)[400r,416r:4)... I schedule the following instruction (48B): 0B BB#0: derived from LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY...

...= [0B,48r:0)[368r,416r:5)... >> R4 = [0B,32r:0)[384r,416r:4)... >> R5 = [0B,32r:0)[400r,416r:4)... >> >> I schedule the following instruction (48B): >> >> 0B BB#0: derived from LLVM BB %entry >> Live Ins: %R0 %R1 %D1 %D2 >> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 >> 12B %vreg30<def> = LDriw <fi#-1>, 0; >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] >> IntRegs:%vreg31 >>...

On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote: > > I've described that issue (see below) when you were out of town... I think > I am getting more context on it. Please take a look... > > So, in short, when the new MI scheduler performs move of an instruction, it > does something like this: > > // Move the instruction to its new

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

...t; R4 = [0B,32r:0)[384r,416r:4)... > >> R5 = [0B,32r:0)[400r,416r:4)... > >> > >> I schedule the following instruction (48B): > >> > >> 0B BB#0: derived from LLVM BB %entry > >> Live Ins: %R0 %R1 %D1 %D2 > >> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > >> 12B %vreg30<def> = LDriw <fi#-1>, 0; > >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > >> IntRe...

...)[352r,416r:5)... > R3 = [0B,48r:0)[368r,416r:5)... > R4 = [0B,32r:0)[384r,416r:4)... > R5 = [0B,32r:0)[400r,416r:4)... > > I schedule the following instruction (48B): > > 0B BB#0: derived from LLVM BB %entry > Live Ins: %R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B...