Displaying 13 results from an estimated 13 matches for "vreg47".
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vreg27
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...PY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
%vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3
%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %25
Predecessors a...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...80B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
432B%vreg49<def> = COPY %vreg13<kil...
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t;; R600_Reg128:%vreg1,%vreg26
> %vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
> %vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> %vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> %vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> %vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3
> %vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...6r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
> 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
> register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
> 432B%vreg49<def> =...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
> ... Some COPYs....
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
> 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
> Successors according to CFG: BB#1
>
>
> // LOOP CON...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...vm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Successors according to CFG: BB#1
// LOOP CONDITION
464B%vreg5<def>...
2017 Jul 27
2
GEP with a null pointer base
...on the same condition,
so the CMP that sets the FLAGS reg in the second select was MCSE’ed to the
earlier CMP in the first select, so here we see the second Select without a CMP:
BB#10: derived from LLVM BB %for.body.5
Predecessors according to CFG: BB#3 BB#9
%vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
//// <=== this SLLI clobbers FLAGS <============
%vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
BCC 2, <BB#12>, %FLAGS<imp-use>...
2017 Jul 28
2
GEP with a null pointer base
...o the CMP that sets the FLAGS reg in the second select was MCSE’ed to the
> earlier CMP in the first select, so here we see the second Select without a CMP:
>
> BB#10: derived from LLVM BB %for.body.5
> Predecessors according to CFG: BB#3 BB#9
> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>
> //// <=== this SLLI clobbers FLAGS <============
> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
> BCC 2, <BB#12>,...
2017 Jul 31
2
GEP with a null pointer base
...the FLAGS reg in the second select was MCSE’ed to the
>> earlier CMP in the first select, so here we see the second Select without a CMP:
>>
>> BB#10: derived from LLVM BB %for.body.5
>> Predecessors according to CFG: BB#3 BB#9
>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>
>> //// <=== this SLLI clobbers FLAGS <============
>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>> BCC 2,...
2017 Jul 31
4
GEP with a null pointer base
...d to
>>> the
>>> earlier CMP in the first select, so here we see the second Select
>>> without a CMP:
>>>
>>> BB#10: derived from LLVM BB %for.body.5
>>> Predecessors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>;
>>> DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>;
>>> DataRegs:%...
2017 Aug 01
0
GEP with a null pointer base
...second select was MCSE’ed to the
>>> earlier CMP in the first select, so here we see the second Select without a CMP:
>>>
>>> BB#10: derived from LLVM BB %for.body.5
>>> Predecessors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>>>...
2017 Jul 24
2
GEP with a null pointer base
> On Jul 21, 2017, at 10:55 PM, Mehdi AMINI <joker.eph at gmail.com> wrote:
>
>
>
> 2017-07-21 22:44 GMT-07:00 Peter Lawrence <peterl95124 at sbcglobal.net <mailto:peterl95124 at sbcglobal.net>>:
> Mehdi,
> Hal’s transformation only kicks in in the *presence* of UB
>
> No, sorry I entirely disagree with this assertion: I believe we