Displaying 19 results from an estimated 19 matches for "vreg46".
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2015 Apr 17
2
[LLVMdev] Multiple connected components in live interval
...ericsson.com> wrote:
>
> Hi,
>
> thanks for answering, but the COPY is there already from after isel. It is a copy of a subreg, after a a call returning 64 bits.
>
> call <ga:@safe_div_func_uint64_t_u_u>
> %vreg45<def> = COPY %r0
> %vreg46<def> = COPY %r1
> %vreg3<def> = COPY %vreg46 <<<<<<<<<<<<<<<<<<
> ST %vreg46, %vreg0
> ST %vreg46, %vreg1
> brr_uncond <BB#4>
>
> Does this ring any bell? Could there...
2015 Apr 16
2
[LLVMdev] Multiple connected components in live interval
...d by the verifier. Does this mean that there should never be
>> any ValNos in a LiveInterval that are not connected? In other words should such an LI never exist, but rather two different LIs?
>
> That’s right. It looks like a copy was inserted,
>
>> %vreg3<def> = COPY %vreg46
>
>
> breaking the live interval, and a new LI was not created. Maybe the splitter did it? You would need to look at debug-only=regalloc.
>
> Andy
>
>>
>> I have tried to run this on in-tree targets, but unfortunately they did not reproduce the condition.
>>...
2015 Apr 20
2
[LLVMdev] Multiple connected components in live interval
...>
>>> thanks for answering, but the COPY is there already from after isel. It is a copy of a subreg, after a a call returning 64 bits.
>>>
>>> call <ga:@safe_div_func_uint64_t_u_u>
>>> %vreg45<def> = COPY %r0
>>> %vreg46<def> = COPY %r1
>>> %vreg3<def> = COPY %vreg46 <<<<<<<<<<<<<<<<<<
>>> ST %vreg46, %vreg0
>>> ST %vreg46, %vreg1
>>> brr_uncond <BB#4>
>>>
&g...
2015 Apr 16
2
[LLVMdev] Multiple connected components in live interval
...#1 BB#4
vreg7<def> = PHI %vreg29, <BB#1>, %vreg4, <BB#4>
...
Successors according to CFG: BB#2 BB#6
BB#2:
Predecessors according to CFG: BB#5
...
Successors according to CFG: BB#3 BB#4
BB#3:
Predecessors according to CFG: BB#2
call()
%vreg46<def> = COPY %return_reg
%vreg3<def> = COPY %vreg46;
use of %vreg 46
Successors according to CFG: BB#4
BB#4:
Predecessors according to CFG: BB#2 BB#3
%vreg4<def> = PHI %vreg7, <BB#2>, %vreg3, <BB#3>
Successors according to CFG: BB#5
Th...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
..._Reg32:%vreg43
%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1
%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
RETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>, %T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
> %T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
> %vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
> %T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
> %vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1
> %T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
> RETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>, %T1_X<imp-use>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...gt; = COPY %vreg43; R600_Reg32:%vreg43
%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
%T1_Y<def> = COPY %vreg44; R600_Reg32:%vreg44
%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
%T1_Z<def> = COPY %vreg45; R600_Reg32:%vreg45
%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 R600_Reg128:%vreg1
%T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46
RETURN
BB#3: derived from LLVM BB %41
Predecessors according to CFG: BB#1
%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
%vreg33<def> =...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...Reg32:%vreg43
> %vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
> %T1_Y<def> = COPY %vreg44; R600_Reg32:%vreg44
> %vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
> %T1_Z<def> = COPY %vreg45; R600_Reg32:%vreg45
> %vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 R600_Reg128:%vreg1
> %T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46
> RETURN
>
> BB#3: derived from LLVM BB %41
> Predecessors according to CFG: BB#1
> %vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg1...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...he stalls are.
>
There are actually 31 resources defined for loads. However, there
aren't actually 31 load units in the hardware. There is 1 load unit
that can hold up to 31 loads waiting to be executed, but only 1 load
can be executed at a time.
Pick Top CLUSTER
Scheduling SU(43) %vreg46<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 48; mem:LD4[<unknown>] SGPR_32:%vreg46 SReg_128:%vreg9
SReg_32: 45 > 44(+ 0 livethru)
VS_32: 51 > 18(+ 0 livethru)
Ready @46c
HWLGKM +1x105u
TopQ.A BotLatency SU(43) 78c
*** Max MOps 1 at cycle 46
Cycle: 47 TopQ.A
TopQ.A @47c
Re...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...128:%vreg1
register: %vreg44 +[768r,784r:0)
784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
register: %vreg45 +[800r,816r:0)
816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1
register: %vreg46 +[832r,848r:0)
848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...768r,784r:0)
> 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
> 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45
> R600_Reg128:%vreg1
> register: %vreg45 +[800r,816r:0)
> 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
> 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46
> R600_Reg128:%vreg1
> register: %vreg46 +[832r,848r:0)
> 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
> 864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>,
> %T1_Y<imp-use,kill>...
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
Hi,
I have a program with over 100 loads (each with a 10 cycle latency)
at the beginning of the program, and I can't figure out how to get
the machine scheduler to intermix ALU instructions with the loads to
effectively hide the latency.
It seems the issue is with load clustering. I restrict load clustering
to 4 at a time, but when I look at the debug output, the loads are
always being
2017 Jul 27
2
GEP with a null pointer base
...hout a CMP:
BB#10: derived from LLVM BB %for.body.5
Predecessors according to CFG: BB#3 BB#9
%vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
//// <=== this SLLI clobbers FLAGS <============
%vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
BCC 2, <BB#12>, %FLAGS<imp-use>
Successors according to CFG: BB#11 BB#12
The problem is that Machine Code Sinking put an “SLLI" instruction, that
modifies the FLAGS registers, in between...
2017 Jul 28
2
GEP with a null pointer base
...ed from LLVM BB %for.body.5
> Predecessors according to CFG: BB#3 BB#9
> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>
> //// <=== this SLLI clobbers FLAGS <============
> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
> BCC 2, <BB#12>, %FLAGS<imp-use>
> Successors according to CFG: BB#11 BB#12
>
>
> The problem is that Machine Code Sinking put an “SLLI" instruction, that
> modifies t...
2017 Jul 31
2
GEP with a null pointer base
....body.5
>> Predecessors according to CFG: BB#3 BB#9
>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>
>> //// <=== this SLLI clobbers FLAGS <============
>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>> BCC 2, <BB#12>, %FLAGS<imp-use>
>> Successors according to CFG: BB#11 BB#12
>>
>>
>> The problem is that Machine Code Sinking put an “SLLI" instruction,...
2017 Jul 31
4
GEP with a null pointer base
...ssors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>;
>>> DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>;
>>> DataRegs:%vreg46,%vreg5
>>> BCC 2, <BB#12>, %FLAGS<imp-use>
>>> Successors according to CFG: BB#11 BB#12
>>>
>>>
>>> The problem is that Machine Code Sinking pu...
2017 Aug 01
0
GEP with a null pointer base
...Predecessors according to CFG: BB#3 BB#9
>>> %vreg49<def> = PHI %vreg47, <BB#9>, %vreg48, <BB#3>; DataRegs:%vreg49,%vreg47,%vreg48
>>>
>>> //// <=== this SLLI clobbers FLAGS <============
>>> %vreg46<def> = SLLI %vreg5, 1, %FLAGS<imp-def,dead>; DataRegs:%vreg46,%vreg5
>>> BCC 2, <BB#12>, %FLAGS<imp-use>
>>> Successors according to CFG: BB#11 BB#12
>>>
>>>
>>> The problem is that Machine Code Sinking put an “SLLI&...
2017 Jul 24
2
GEP with a null pointer base
> On Jul 21, 2017, at 10:55 PM, Mehdi AMINI <joker.eph at gmail.com> wrote:
>
>
>
> 2017-07-21 22:44 GMT-07:00 Peter Lawrence <peterl95124 at sbcglobal.net <mailto:peterl95124 at sbcglobal.net>>:
> Mehdi,
> Hal’s transformation only kicks in in the *presence* of UB
>
> No, sorry I entirely disagree with this assertion: I believe we