search for: vreg4

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2014 Aug 15
3
[LLVMdev] Is it possible to tie two defs together?
For example, if you have something like: .... vreg3 = LD operation vreg4 = vreg2 * vreg1 ... Where I would like vreg3 and vreg4 to map to the same physical register? Imagine that the second instruction has an implicit arithmetic operation tied to vreg 4 such that vreg4 is both an input and output and the initial value of vreg4 is loaded into vreg3, so such that vreg4...
2014 Oct 24
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi! During my backend development I get the error message for some tests: *** Bad machine code: Virtual register def doesn't dominate all uses. *** (C source-code, byte-code disassembly and printed machine code at the end of the email) The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code. One possible reason could be that I haven't implemented all operations, eg I didn't implement MUL at this stage. Their "state" is LEGAL and not CUS...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...t; = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0 32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2 48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2 64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3 80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5 96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffse...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...efore phi elimination this code looks much more sane: > > # *** IR Dump After Live Variable Analysis ***: > # Machine code for function push: SSA > Function Live Outs: %R0 > > BB#0: derived from LLVM BB %entry > %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 > %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 > Successors according to CFG: BB#1 > > BB#1: derived from LLVM BB %for.cond > Predecessors according to CFG: BB#0 BB#1 > %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,...
2012 Jan 19
4
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
...quot;-disable-cross-class-join" to be sure the resulting code is ok? I have several cases where cross class joins are carried out that makes the code turn out illegal, because the "new" register class is not allowed in all instructions where it is now used. For example, by joining %vreg4, %vreg7 and %vreg9 the following code %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 is turned into %vreg17<def>...
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
...During my backend development I get the error message for some tests: >> *** Bad machine code: Virtual register def doesn't dominate all uses. *** >> >> (C source-code, byte-code disassembly and printed machine code at the end of the email) >> >> The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code. >> >> One possible reason could be that I haven't implemented all operations, eg I didn't implement MUL at this stage. Their "state" is...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...pointer. Bad, but perfectly valid code. In SSA it looked like this: BB#0: derived from LLVM BB %entry %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def. %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %for.cond Predecessors according to CFG: BB#0 BB#1 %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 %vreg1&l...
2014 Oct 31
2
[LLVMdev] Virtual register def doesn't dominate all uses
...error message for some tests: >>>> *** Bad machine code: Virtual register def doesn't dominate all uses. *** >>>> >>>> (C source-code, byte-code disassembly and printed machine code at the end of the email) >>>> >>>> The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code. >>>> >>>> One possible reason could be that I haven't implemented all operations, eg I didn't implement MUL at this stage. Their &quo...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...perfectly valid code. > > In SSA it looked like this: > BB#0: derived from LLVM BB %entry > %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def. > %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 > Successors according to CFG: BB#1 > > BB#1: derived from LLVM BB %for.cond > Predecessors according to CFG: BB#0 BB#1 > %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...%T2_Y %T2_X BB#0: derived from LLVM BB %0     Live Ins: %T1_W %T1_Z %T1_Y %T1_X %vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3 %vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2 %vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1 %vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0 RESERVE_REG 0 %vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3 %vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5 %vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5 %vreg7<def> = F...
2012 Jan 19
0
[LLVMdev] Problem with cross class joins in the RegisterCoalescer
..." to be sure the resulting code is ok? No. > I have several cases where cross class joins are carried out that makes > the code turn out illegal, because the "new" register class is not > allowed in all instructions where it is now used. > > For example, by joining %vreg4, %vreg7 and %vreg9 the following code > > %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 > %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 > %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 > > is turned into...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...ly right here - look at this - before phi elimination this code looks much more sane: # *** IR Dump After Live Variable Analysis ***: # Machine code for function push: SSA Function Live Outs: %R0 BB#0: derived from LLVM BB %entry %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %for.cond Predecessors according to CFG: BB#0 BB#1 %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 %vreg1&l...
2016 Mar 18
3
generate vectorized code
...32 = extract_vector_elt 0x6a85388, 0x6a813b0 [ORD=9] [ID=16] 0x6a85388: v4i32 = add 0x6a81098, 0x6a81e00 [ORD=8] [ID=15] 0x6a81098: v4i32 = add 0x6a81bf0, 0x6a84168 [ORD=6] [ID=12] 0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5] [ID=8] 0x6a819e0: v4i32 = Register %vreg4 [ID=1] 0x6a84168: v4i32 = vector_shuffle 0x6a81bf0, 0x6a857a8<2,3,u,u> [ORD=5] [ID=10] 0x6a81bf0: v4i32,ch = CopyFromReg 0x6a2b7f0, 0x6a819e0 [ORD=5] [ID=8] 0x6a819e0: v4i32 = Register %vreg4 [ID=1] 0x6a857a8: v4i32 = undef [ID=2] 0x6a81e00: v4i32 = vector_...
2015 Nov 25
2
need help for customized backend LowerFormalArguments
...However, when I use llc and print-after-all to check the machine instructions. At very beginning, the machine instructions look like this: %vreg1<def> = COPY %P1; PRegs:%vreg1 %vreg0<def> = COPY %P0; PRegs:%vreg0 %vreg3<def> = COPY %vreg0; GRRegsAdditional:%vreg3 PRegs:%vreg0 %vreg4<def> = COPY %vreg1; GRRegsAdditional:%vreg4 PRegs:%vreg1 %vreg2<def> = ADDINT %vreg3, %vreg4; GRRegsAdditional:%vreg2,%vreg3,%vreg4 %R10<def> = COPY %vreg2; GRRegsAdditional:%vreg2 RET %R10 And after "Post-RA pseudo instruction expansion pass", it looks like this Functi...
2016 Feb 20
2
[VSXFMAMutate] OldFMAReg may be wrongly rewritten
...since OldFMAReg (%vreg12 in debug info) is actually defined in two blocks. I wonder if we can fix this by making the transformation simpler, that is, instead of doing: %vreg12<def> = COPY %vreg7; VSSRC:%vreg12,%vreg7 %vreg12<def,tied1> = XSMADDASP %vreg12<tied0>, %vreg0, %vreg4; VSSRC:%vreg12,%vreg0 F4RC:%vreg4 -> %vreg0<def,tied1> = XSMADDMSP %vreg0<tied0>, %vreg4, %vreg7; VSSRC:%vreg0,%vreg7 F4RC:%vreg4 , we do: %vreg12<def> = COPY %vreg7; VSSRC:%vreg12,%vreg7 %vreg12<def,tied1> = XSMADDASP %vreg12<tied0>, %vreg0, %vreg4; VSS...
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
...t;>>> *** Bad machine code: Virtual register def doesn't dominate all uses. *** >>>>>> >>>>>> (C source-code, byte-code disassembly and printed machine code at the end of the email) >>>>>> >>>>>> The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code. >>>>>> >>>>>> One possible reason could be that I haven't implemented all operations, eg I didn't implement MUL at this s...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
...<def> = COPY %R25R24<kill>; PTRREGS:%vreg8 updated: 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 Joined. Result = %R25R24,inf = [0L,96d:0) 0 at 0L-phidef 32L %vreg5<def> = COPY %R25R24; PTRREGS:%vreg5 Not coalescable. 64L %vreg6<def> = COPY %vreg4<kill>; DLDREGS:%vreg6,%vreg4 Considering merging %vreg4 with %vreg6 to DLDREGS RHS = %vreg4 = [48d,64d:0) 0 at 48d LHS = %vreg6 = [64d,80d:1)[80d,112d:0) 0 at 80d 1 at 64d updated: 48L %vreg6<def> = LDWRd %vreg5<kill>; mem:LD2[%a](align=1)(tbaa=!&q...
2013 May 13
1
[LLVMdev] Tracking down a SELECT expansion to predicated moves
...try %vreg0<def> = MOVL_GA <ga:@b>; GR:%vreg0 %vreg1<def> = LDSHri %vreg0<kill>, 0; mem:LD4[@b] GR:%vreg1,%vreg0 %vreg2<def> = MOVIMM21 0; GR:%vreg2 %vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2 %vreg4<def> = MOVIMM21 8; GR:%vreg4 %vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4 %vreg6<def> = MOVIMM21 23; GR:%vreg6 %vreg7<def,tied1> = CMOV %vreg5<tied0>, %vreg6<kill>, %vreg3<kill>; GR:%vreg7,%vreg5,%vreg6 PR:%vreg3 %v...
2015 Apr 16
2
[LLVMdev] Multiple connected components in live interval
...- with -O3 it just returns zero. It contains two nested loops, with a call inside the inner loop, which is a CFG-diamond. The PHI-nodes look like this in the inner loop: BB#5: // Inner loop header Predecessors according to CFG: BB#1 BB#4 vreg7<def> = PHI %vreg29, <BB#1>, %vreg4, <BB#4> ... Successors according to CFG: BB#2 BB#6 BB#2: Predecessors according to CFG: BB#5 ... Successors according to CFG: BB#3 BB#4 BB#3: Predecessors according to CFG: BB#2 call() %vreg46<def> = COPY %return_reg %vreg3<def> = CO...