search for: vreg34

...;8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } Here's the tail-end of the log, with debugging turned on: $llc bugpoint.reduced.simplified.bc -debug ... 208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34 Considering merging to VecRegs with %vreg34 in %vreg13 RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and vreg48 are joined. It's right. > > But joining the following copy > > 912B%vreg32:sel_x<de...

When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. If I look at the : %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 instructions ; it gets joined to : 928B%vreg34<def> = COPY %vreg48:sel_y;  when vreg6 and vreg48 are joined. It's right. But joining the following copy  912B%vreg32:sel_x<def,read-undef> = COPY %vreg48:sel_x;...

...Reg32:%vreg30 560BJUMP <BB#3>, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg // LOOP BODY 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 976B%vreg36<def> = COPY %vreg35<kill>; R60...

...#3>, pred:%PREDICATE_BIT > 576BJUMP <BB#2>, pred:%noreg > > // LOOP BODY > 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 > 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 > 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 > 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 > 976B%vreg36<def> = COPY %vreg35&l...

...t;imp-use,kill> BB#3:# derived from  896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 register: %vreg31 +[896r,912r:0) 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 register: %vreg32 +[912r,944r:0) 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 register: %vreg34 +[928r,960r:0) 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 register: %vreg35 +[944r,976r:0) 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Re...

...gisterCoalescing Pass seems to ignore part of CFG. > > Hi Vincent, > > On 25/10/2012 18:14, Vincent Lejeune wrote: >> When examining the debug output of regalloc, it seems that joining 32bits > reg also joins 128 parent reg. >> >> If I look at the : >> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 > R600_Reg128:%vreg6 >> >> instructions ; it gets joined to : >> 928B%vreg34<def> = COPY %vreg48:sel_y; >> >> when vreg6 and vreg48 are joined. It's right. >> >> But joining the followi...

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

...re part of CFG. >> >> Hi Vincent, >> >> On 25/10/2012 18:14, Vincent Lejeune wrote: >>> When examining the debug output of regalloc, it seems that joining 32bits >> reg also joins 128 parent reg. >>> >>> If I look at the : >>> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 >> R600_Reg128:%vreg6 >>> >>> instructions ; it gets joined to : >>> 928B%vreg34<def> = COPY %vreg48:sel_y; >>> >>> when vreg6 and vreg48 are joined. It's right. >>> >&g...