search for: vreg3

...6)   %24 = extractelement <4 x float> %9, i32 3   call void @llvm.AMDGPU.store.output(float %24, i32 7)   ret void } # *** IR Dump Before Expand ISel Pseudo-instructions ***: # Machine code for function main: SSA Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3 Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X BB#0: derived from LLVM BB %0     Live Ins: %T1_W %T1_Z %T1_Y %T1_X %vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3 %vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2 %vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1 %vreg0&lt...

For example, if you have something like: .... vreg3 = LD operation vreg4 = vreg2 * vreg1 ... Where I would like vreg3 and vreg4 to map to the same physical register? Imagine that the second instruction has an implicit arithmetic operation tied to vreg 4 such that vreg4 is both an input and output and the initial value of vreg4 is loaded into vreg3...

...ost SSA Function Live Ins: %FA_ROFF1 in %vreg0 0B BB#0: derived from LLVM BB %entry Live Ins: %FA_ROFF1 16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0 32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2 48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2 64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3 80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FP...

...MPLICIT_DEF; IntRegs:%vreg5 > %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 > Successors according to CFG: BB#1 > > BB#1: derived from LLVM BB %for.cond > Predecessors according to CFG: BB#0 BB#1 > %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 > %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 > %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0 > %vreg3<def> = ADD_ri %vreg2, 8; I...

...////////////////////////// int i = a; do { // loop body --i; } while (i != 0); ////////////////////////// After code selection I've something like: BB0: %vreg0<def> = COPY %R0; // R0 contains 'a' J <#BB1> BB1: %vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3> J <#BB2> BB2: // loop body BB3: %vreg3<def> = ADDI %vreg1<kill>, 1 CMPNE %vreg3, 0, %SR<implicit,def> JNZ <#BB1> J <#BB4> BB4: // end With the optimization pass I replace the decrement, comparison and conditional jump with the...

...ers. > b) The first two are in a consecutive pair (second > first) > c) The second two are in a consecutive pair (fourth > third) Constraints b & c are OK, but a is too strict : "mpra %R0, %R1, %R0, %R1" is OK. But I though, may be wrongly, that "mpra %vreg1, %vreg2, %vreg3, %vreg4" meant %vreg1 and %vreg3 will be allocated to different physical registers, or they would have been coalesced. For example, the pass I added after the coalescer ensures that instructions like "mpra %vreg1, %vreg2, %vreg1, %vreg4" (impossible for pbqp to solve) is transformed...

...%vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %for.cond Predecessors according to CFG: BB#0 BB#1 %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg2,%vreg0 %vreg3<def> = ADD_ri %vreg2, 8; IntRegs:%vreg...

...;<<<<<<<<<<Dummy def. %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 Successors according to CFG: BB#1 BB#1: derived from LLVM BB %for.cond Predecessors according to CFG: BB#0 BB#1 %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value. %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in] IntRegs:...

...;<<<<Dummy def. > %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4 > Successors according to CFG: BB#1 > > BB#1: derived from LLVM BB %for.cond > Predecessors according to CFG: BB#0 BB#1 > %vreg0<def> = PHI %vreg4, <BB#0>, %vreg3, <BB#1>; IntRegs:%vreg0,%vreg4,%vreg3 > %vreg1<def> = PHI %vreg5, <BB#0>, %vreg2, <BB#1>; IntRegs:%vreg1,%vreg5,%vreg2 <<<<<<<<<<< Use of that dummy value. > %vreg2<def> = LDriw %vreg0<kill>, 0; mem:LD4[%stack.0.in]...

Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that. I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged. vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives...

...i32:$dst, (add i32:$src1, i32:$src2))]>; I assume this could work. However, when I use llc and print-after-all to check the machine instructions. At very beginning, the machine instructions look like this: %vreg1<def> = COPY %P1; PRegs:%vreg1 %vreg0<def> = COPY %P0; PRegs:%vreg0 %vreg3<def> = COPY %vreg0; GRRegsAdditional:%vreg3 PRegs:%vreg0 %vreg4<def> = COPY %vreg1; GRRegsAdditional:%vreg4 PRegs:%vreg1 %vreg2<def> = ADDINT %vreg3, %vreg4; GRRegsAdditional:%vreg2,%vreg3,%vreg4 %R10<def> = COPY %vreg2; GRRegsAdditional:%vreg2 RET %R10 And after "Post-...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and vreg48 are joined. It's right. > > But joining the following copy > > 912B%vreg32:sel_x<d...

Vincent, File a bug report so you can get a fix for it. Ivan On 25/10/2012 23:01, Vincent Lejeune wrote: > Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that. > I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged. > vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vr...

...u $reg1,$reg2,$zero //Transfer the completed shift data to the original destination register > > Since you guys mentioned that the MI are represented in MachineSSA form, i imagined my routine represented by virtual registers would look something like this: > > andi $vreg3,$vreg3,0x1f > #BB_1: beq $vreg3,$zero,#BB_2 > sub $vreg3,$vreg3,1 > sll $vreg2,$vreg2,1 > j #BB_1 > #BB_2: addu $vreg1,$vreg2,$zero > > With the -verify-ma...

...d the LDRi12 instructions to use a GPRPair sub-register. The copy into %vreg4 asserts because of the two definitions of vreg9, coming from vreg9:gsub_0 and vreg9:gsub_1. %vreg1<def> = COPY %R1; GPR:%vreg1 %vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2 %vreg3<def> = ADDrsi %vreg2<kill>, %vreg1, 18, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg3,%vreg2,%vreg1 %vreg9:gsub_0<def,read-undef> = LDRi12 %vreg3, 112, pred:14, pred:%noreg; mem:LD4[%arrayidx83](tbaa=!"int") GPRPair:%vreg9 :%vreg3 %vreg9:gsub_1<def,re...

...dy > --i; > } while (i != 0); > ////////////////////////// > > > After code selection I've something like: > > BB0: > %vreg0<def> = COPY %R0; // R0 contains 'a' > J <#BB1> > BB1: > %vreg1<def> = PHI %vreg0, <#BB0>, %vreg3, <#BB3> > J <#BB2> > BB2: > // loop body > BB3: > %vreg3<def> = ADDI %vreg1<kill>, 1 > CMPNE %vreg3, 0, %SR<implicit,def> > JNZ <#BB1> > J <#BB4> > BB4: > // end > > With the optimization pass I repla...

...39;s basically a main function with a printf and a return inside it): # Machine code for function main: SSA BB#0: derived from LLVM BB %entry ADJCALLSTACKDOWN64 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg2<def> = MOV32ri64 <ga:@str>; GR32:%vreg2 %vreg3<def> = SUBREG_TO_REG 0, %vreg2<kill>, 4; GR64:%vreg3 GR32:%vreg2 %RDI<def> = COPY %vreg3; GR64:%vreg3 CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>...

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

...chine code for function main: SSA Function Live Outs: %r8 BB#0: derived from LLVM BB %entry %vreg0<def> = MOVL_GA <ga:@b>; GR:%vreg0 %vreg1<def> = LDSHri %vreg0<kill>, 0; mem:LD4[@b] GR:%vreg1,%vreg0 %vreg2<def> = MOVIMM21 0; GR:%vreg2 %vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2 %vreg4<def> = MOVIMM21 8; GR:%vreg4 %vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4 %vreg6<def> = MOVIMM21 23; GR:%vreg6 %vreg7<def,tied1> = CMOV %vreg5<tied0&...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several