Displaying 20 results from an estimated 27 matches for "vreg29".
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2017 Feb 02
3
Register allocator behaves differently when compiling with and without -g
...cator, the code is
identical when compiling with and without -g (with the exception of "
DBG_VALUE" instructions). The only difference I can see is the value
assigned to the slot index for each instruction. As an example, without -g
a snippet of a basic block looks like this:
32B %vreg29<def> = LDImm 1; REG1:%vreg29
36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
44B %vreg68<def> = LDImm 12345; REG1:%vreg68
64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; R...
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
...e code is identical when compiling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29
> 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
> 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
> 44B %vreg68<def> = LDImm 12345; REG1:%vreg68
> 64B %vreg143:vsub32_0<def> = COPY...
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
...e code is identical when compiling with and without -g (with the exception of "DBG_VALUE" instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this:
>
> 32B %vreg29<def> = LDImm 1; REG1:%vreg29
> 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44
> 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143
> 44B %vreg68<def> = LDImm 12345; REG1:%vreg68
> 64B %vreg143:vsub32_0<def> = COPY...
2011 May 02
2
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
...rtion `BI.FirstUse >= Start'
failed.
The following is the Machine IR and LiveVariables::ValInfo dump before and
after PHI nodes elimination.
1. Before PHI nodes elimination.
-Machine IR:
BB#14: derived from LLVM BB %for.cond151.preheader
Predecessors according to CFG: BB#12 BB#13
%vreg29<def> = PHI %vreg25, <BB#12>, %vreg28, <BB#13>;
CPURegs:%vreg29,%vreg25,%vreg28
%vreg30<def> = PHI %vreg26, <BB#12>, %vreg27, <BB#13>;
CPURegs:%vreg30,%vreg26,%vreg27
BNE %vreg81<kill>, %ZERO, <BB#17>; CPURegs:%vreg81
J <BB#15>
Su...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
9...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...gt; 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Need...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg13
Successors according to CFG: BB#1
// LOOP CONDITION
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...to CFG: BB#1
>
>
> // LOOP CONDITION
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
> 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...edStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move a...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
>> 28B %vreg106<def> = TFRI 16777216;
>> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
>> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
>> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...+[464r,592B:0) +[880B,992r:0)
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
register: %vreg29 +[512r,528r:0)
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
register: %vreg30 +[528r,544r:0)
544B%PREDICATE_BIT<...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...2r:0)
> 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
> register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
> register: %vreg29 +[512r,528r:0)
> 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
> register: %vreg30 +[528r,544r:0)...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...eg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> >> 28B %vreg106<def> = TFRI 16777216;
> >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> >> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> >> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> >> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<&...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...gt; 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop
> 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Need...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
Andy,
I've described that issue (see below) when you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {