Displaying 2 results from an estimated 2 matches for "vreg267".
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vreg26
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7 >, %RA<imp-def,dead>, %D6<imp-use,kill>, %SP<imp-def>, %D0<imp-def>
4768B ADJCALLSTACKUP 16, 0, %SP<imp-def>, %SP<imp-use>
4784B %vreg267<def> = COPY %D0<kill>; AFGR64:%vreg267
4800B %vreg268<def> = FMUL_D32 %vreg257, %vreg267; AFGR64:%vreg268,%vreg257,%vreg267
4816B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use>
4832B %vreg269<def> = FMUL_D32 %vreg0, %vreg264; AFGR64:%vreg269,%vreg0,%vreg264
4...
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered.
- Matthias
> On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote:
>
> I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet.
>
> The