search for: vreg26

...%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 %vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 %vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 %vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 %vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...f> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 > %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 > %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 > %vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 > %vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 > %vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 > %vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 > %vreg27:sel_z<def> = COPY %vreg25<kill&g...

...4 +[176r,256r:0) 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2 register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 register: %vreg25 +[208r,272r:0) 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 register: %vreg26 +[224r,336r:0) 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0)  0 at 240r 1 at...

..._y<def> = COPY %vreg2; R600_Reg128:%vreg24 > R600_Reg32:%vreg2 > register: %vreg24 replace range with [176r,192r:1) RESULT: > [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r > 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 > register: %vreg25 +[208r,272r:0) > 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 > register: %vreg26 +[224r,336r:0) > 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 > R600_TReg32:%vreg16 > register: %vreg26 replace range with [224r,240r:1) RESULT: > [224r,240r:1)[24...

...LLVM BB %entry Live Ins: %R0 %R1 %D1 %D2 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 48B...

...INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15 > %vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2 > %vreg25<def> = R600_LOAD_CONST 6; R600_Reg32:%vreg25 > %vreg26<def,tied1> = INSERT_SUBREG %vreg23<tied0>, %vreg16, sel_z; R600_Reg128:%vreg26,%vreg23 R600_TReg32:%vreg16 > RESERVE_REG 1 > %vreg27<def,tied1> = INSERT_SUBREG %vreg24<tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25 > %vreg28<de...

...def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15 %vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2 %vreg25<def> = R600_LOAD_CONST 6; R600_Reg32:%vreg25 %vreg26<def,tied1> = INSERT_SUBREG %vreg23<tied0>, %vreg16, sel_z; R600_Reg128:%vreg26,%vreg23 R600_TReg32:%vreg16 RESERVE_REG 1 %vreg27<def,tied1> = INSERT_SUBREG %vreg24<tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25 %vreg28<def> = R600_LO...

...lt;def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D...

...240B JUMP <BB#3>, pred:%vreg24; PredRegs:%vreg24 Successors according to CFG: BB#6(12) BB#3(20) 256B BB#6: Predecessors according to CFG: BB#2 288B JUMP <BB#5>, pred:%noreg Successors according to CFG: BB#5 304B BB#3: Predecessors according to CFG: BB#2 336B %vreg26<def> = COPY %P0; IntRegs:%vreg26 Successors according to CFG: BB#4 352B BB#4: derived from LLVM BB %while.body Predecessors according to CFG: BB#4 BB#3 400B %vreg14<def> = LDUBrr %vreg8, 0, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 0)] IntR...

...8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>;...

On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote: > The code in collectRanges() does: > > // Collect ranges for register units. These live ranges are computed on > // demand, so just skip any that haven't been computed yet. > if (TargetRegisterInfo::isPhysicalRegister(Reg)) { > for (MCRegUnitIterator Units(Reg,

...%R0 %R1 %D1 %D2 > 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D2<kill>; DoubleR...

The code in collectRanges() does: // Collect ranges for register units. These live ranges are computed on // demand, so just skip any that haven't been computed yet. if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))

...8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27 12B %vreg30<def> = LDriw <fi#-1>, 0; mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 28B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop 32B %vreg29<def> = COPY %D2<kill>;...

...OPY %R1<kill>; IntRegs:%vreg27 >> 12B %vreg30<def> = LDriw <fi#-1>, 0; >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] >> IntRegs:%vreg31 >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 >> 28B %vreg106<def> = TFRI 16777216; >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop >> 32B %vreg29<def> =...

On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote: > > I've described that issue (see below) when you were out of town... I think > I am getting more context on it. Please take a look... > > So, in short, when the new MI scheduler performs move of an instruction, it > does something like this: > > // Move the instruction to its new

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

...egs:%vreg27 > >> 12B %vreg30<def> = LDriw <fi#-1>, 0; > >> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > >> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > >> IntRegs:%vreg31 > >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > >> 28B %vreg106<def> = TFRI 16777216; > >> IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > >> 32B %vreg...

...lt;def> = COPY %R1<kill>; IntRegs:%vreg27 > 12B %vreg30<def> = LDriw <fi#-1>, 0; > mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30 > 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 28B %vreg106<def> = TFRI 16777216; > IntRegs:%vreg106<<<<<<<<<<<<<<<<<<<<<<<<<<< CurrentTop > 32B %vreg29<def> = COPY %D...