Displaying 2 results from an estimated 2 matches for "vreg261".
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2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...ke this issue isn't Mips specific.
Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask):
4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253
4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248
4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use>
4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243
4544B JAL <ga:@sin>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F2...
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered.
- Matthias
> On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote:
>
> I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet.
>
> The