Displaying 2 results from an estimated 2 matches for "vreg206".
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2016 Apr 28
4
Assertion in MachineScheduler.cpp
...ing to CFG: BB#43 BB#44
DBG_VALUE %vreg287, %noreg, !"base"
%vreg203<def> = LWZ <fi#5>, 0; mem:LD4[%args] GPR:%vreg203
%vreg204<def> = ADDI %vreg203, 3; GPR:%vreg204,%vreg203
--> %vreg205<def> = ADDI %R0, -4; GPR:%vreg205
%vreg206<def> = AND %vreg204, %vreg205;
GPR:%vreg206,%vreg204,%vreg205
%vreg207<def> = ADDI %vreg206, 4; GPR:%vreg207,%vreg206
%vreg290<def> = LWZ %vreg206, 0; mem:LD4[<unknown>]
GPR:%vreg290,%vreg206
SFGTS_ri %vreg290, -1, %SR<imp-def>; GPR:%vreg29...
2016 Apr 27
2
Assertion in MachineScheduler.cpp
Apologies if my questions sound dumb. They are provided below.
On Wed, Apr 27, 2016 at 2:43 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> Are there any instructions (other than COPY) that use hardware
> (allocatable) registers?
>
How do I find that out?
> Could you show the instructions in the scheduling range?
>
How can I see instructions in the current