search for: vreg20

Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> = REG_SEQUENCE %vreg2, hi16, %...

...ell, this works as every register are still virtual when lowering custom Emitter instructions. However the RegisterCoalescer pass does not preserve TargetFlag in the JoinCopy() member function. For instance, here is some output of the regalloc pass (TF=2 corresponds to a Neg TargetFlag) : 352B    %vreg20:sel_x<def,undef> = COPY %vreg16<kill>[TF=2], %vreg20<imp-def>; R600_Reg128:%vreg20 R600_Reg32:%vreg16     Considering merging %vreg16 with %vreg20:sel_x     Cross-class to R600_Reg128.         RHS = %vreg16 = [304r,352r:0)  0 at 304r         LHS = %vreg20 = [352r,400r:0)  0 at 352...

...8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:%vreg4,%vreg2,%vreg3 432B %vreg9<def> = DIVD %vreg7, %vreg8; G8RC:%vreg9,%vreg7,%vreg8 440B %vreg12<def&g...

...ns: %T1_X %T1_Y %T1_Z %T1_W %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18 %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20 %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14 %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22 %vreg21<de...

On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote: > ********** EXPANDING POST-RA PSEUDO INSTRS ********** > ********** Function: main > real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, > %D7<imp-def> > replaced by: %R15<def> = TFR %R4, %D7<imp-def> > > The R4 is a subreg of D2 double

...t; %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 > %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 > %vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14 > %vreg18<def> = R600_LOAD_CONST 4; R600_Reg32:%vreg18 > %vreg20<def> = IMPLICIT_DEF; R600_Reg128:%vreg20 > %vreg19<def,tied1> = INSERT_SUBREG %vreg20<tied0>, %vreg14, sel_x; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14 > %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 > %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg2...

..._NOX0:%vreg0 >> 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 >> 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 >> 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 >> 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:%vreg4,%vreg2,%vreg3 >> 432B %vreg9<def> = DIVD %vreg7, %vreg8; G8RC:%vreg9,%vreg7,%vreg8 >> 440B...

Hello everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def> replaced by:

...R16:%vreg18 %vreg59<def> = ADD16rm %vreg58<kill>, <fi#1>, 16, %EX<imp-def>; mem:LD1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59,%vreg58 MOV16mr <fi#1>, 16, %vreg59; mem:ST1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59 %vreg20<def> = COPY %vreg59; GEXR16:%vreg20 GR16:%vreg59 %vreg21<def> = MOV16rm <fi#1>, 15; mem:LD1[%sunkaddr24](tbaa=!"int") GEXR16:%vreg21 %vreg81<def> = COPY %vreg21; GEXR16:%vreg81,%vreg21 BR_CCrr 2, %vreg59, %vreg21, <BB#10>; GR16:%vreg59...

...into stuff like this instead: 832B %vreg50:hi16<def,read-undef> = COPY %vreg0 848B ... 864B %vreg19<def,dead> = COPY %vreg50 880B %vreg19:lo16<def,read-undef> = COPY %vreg73 896B ... 912B mv_a32_r16_rmod1 %vreg19, %vreg20 ... *** Bad machine code: Multiple connected components in live interval *** - function: fixedconv - interval: %vreg19 [864r,864d:0)[880r,1024r:1) 0 at 864r 1 at 880r 0: valnos 0 1: valnos 1 So here, both the setting of the hi16 and lo16 parts are marked with read-undef, as wanted. Howev...

...%vreg0 %vreg16<def> = LS64_LDR <fi#-1>, 0; mem:LD8[FixedStack-1](align=16) GPR64:%vreg16 %vreg17<def> = MOVZxii 42, 0; GPR64:%vreg17 LS64_STR %vreg17<kill>, <fi#-2>, 0; mem:ST8[FixedStack-2](align=16) GPR64:%vreg17 %vreg19<def> = IMPLICIT_DEF; GPR64:%vreg19 %vreg20<def> = IMPLICIT_DEF; GPR32:%vreg20 %vreg18<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg20<kill>, sub_32; GPR64:%vreg18,%vreg19 GPR32:%vreg20 %X0<def> = COPY %vreg18; GPR64:%vreg18 %X1<def> = COPY %vreg18; GPR64:%vreg18 %X2<def> = COPY %vreg18; GPR64...

...Register:i64 %vreg18, t19 t20: i64 = extract_vector_elt t16, Constant:i64<3> t32: ch = CopyToReg t0, Register:i64 %vreg19, t20 t21: i64 = extract_vector_elt t16, Constant:i64<4> t34: ch = CopyToReg t0, Register:i64 %vreg20, t21 t22: i64 = extract_vector_elt t16, Constant:i64<5> t36: ch = CopyToReg t0, Register:i64 %vreg21, t22 t23: i64 = extract_vector_elt t16, Constant:i64<6> t38: ch = CopyToReg t0, Register:i64 %vreg22, t23...

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,