Displaying 4 results from an estimated 4 matches for "vreg187".
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vreg17
2013 Feb 08
2
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...ause after
line end the stack pointer is pointing to useful data.
Could anyone working on x86 instruction selection give some pointers to
prevent this?
Thanks,
-Peng
ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>,
%ESP<imp-use> ; line 1
%vreg187<def> = COPY %ESP; GR32:%vreg187
; line 2
MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack]
GR32:%vreg187 FR64:%vreg36 ; line 3
%vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108]...
2013 Feb 08
0
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...ing to useful data.
>
> Could anyone working on x86 instruction selection give some pointers to prevent this?
>
> Thanks,
> -Peng
>
>
> ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1
> %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2
> MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3
> %vreg188<def> = MOV32rm %v...
2012 Feb 10
1
[LLVMdev] Question about /llvm/trunk/lib/CodeGen/MachineScheduler.cpp
...ve things into a header so you can start checking in a Hexagon MachineScheduler pass if you want.
-Andy
> Thanks.
>
> Sergei
>
>
> BB#4: derived from LLVM BB %cond.end
> Predecessors according to CFG: BB#3 BB#2
> %vreg194<def> = ADDr_MPYir_V4 %vreg185, 120, %vreg187<kill>;
> IntRegs:%vreg194,%vreg185,%vreg187
> %vreg195<def> = CONST32_set <ga:@raac_sfBandTabShortOffset>;
> IntRegs:%vreg195
> ....
> %vreg306<def> = TFRI 127; IntRegs:%vreg306
> %vreg307<def> = TFRI 1; IntRegs:%vreg307
> %vreg438<d...
2011 May 02
2
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
...g29<def> = COPY %vreg180<kill>; CPURegs:%vreg29,%vreg180
%vreg30<def> = COPY %vreg181<kill>; CPURegs:%vreg30,%vreg181
BEQ %vreg81, %ZERO, <BB#15>; CPURegs:%vreg81
Successors according to CFG: BB#15 BB#20
BB#20:
Predecessors according to CFG: BB#14
%vreg187<def> = COPY %vreg14<kill>; CPURegs:%vreg187,%vreg14
%vreg188<def> = COPY %vreg29<kill>; CPURegs:%vreg188,%vreg29
J <BB#17>
Successors according to CFG: BB#17
BB#15: derived from LLVM BB %for.body156.preheader
Predecessors according to CFG: BB#14
BB#17...