search for: vreg17

...t;def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15 %T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 %vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 %T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 %vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 %T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 %T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17 %T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3 %T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 %T1_Z<def> = CO...

...;new" register class is not allowed in all instructions where it is now used. For example, by joining %vreg4, %vreg7 and %vreg9 the following code %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 is turned into %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17 aN32_0_7:%vreg4 The load instruction however, can only use registers from the rN class, but the coalescer has changed so it now uses the lo16...

...> allowed in all instructions where it is now used. > > For example, by joining %vreg4, %vreg7 and %vreg9 the following code > > %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 > %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 > %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 > > is turned into > > %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17 > aN32_0_7:%vreg4 > > The load instruction however, can only use registers from the rN class, > but the coales...

...rently even if vreg32 lives in the 4 machine blocks After joining, there are still vreg32 occurence in the machinefunction dump.  Before, the MF dump is : _________________ # Machine code for function main: Post SSA Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17 Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X BB#0: derived from LLVM BB %0     Live Ins: %T1_X %T1_Y %T1_Z %T1_W %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vr...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...in the 4 machine blocks > After joining, there are still vreg32 occurence in the machinefunction dump. > > Before, the MF dump is : > _________________ > # Machine code for function main: Post SSA > Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17 > Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X > > BB#0: derived from LLVM BB %0 > Live Ins: %T1_X %T1_Y %T1_Z %T1_W > %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 > %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> =...

...6, <1 x i32> %55, <1 x i32> <i32 1>   %58 = extractelement <1 x i32> %57, i32 0   br label %25 } # *** IR Dump Before Expand ISel Pseudo-instructions ***: # Machine code for function main: SSA Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17 Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X BB#0: derived from LLVM BB %0     Live Ins: %T1_X %T1_Y %T1_Z %T1_W %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 %vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15 %vr...

...i32> <i32 1> > %58 = extractelement <1 x i32> %57, i32 0 > br label %25 > } > # *** IR Dump Before Expand ISel Pseudo-instructions ***: > # Machine code for function main: SSA > Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17 > Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X > > BB#0: derived from LLVM BB %0 > Live Ins: %T1_X %T1_Y %T1_Z %T1_W > %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17 > %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16 > %vreg15<def> =...

...i32 0)] IntRegs:%vreg14,%vreg8 dbg:../src/getbits.c:56:5 416B STBrr %vreg26, 0, %vreg14<kill>, pred:%noreg; mem:ST1[%p.04] IntRegs:%vreg26,%vreg14 dbg:../src/getbits.c:56:5 432B %vreg27<def> = ADDri %vreg27<kill>, 1, pred:%noreg; IntRegs:%vreg27 dbg:../src/getbits.c:55:5 448B %vreg17<def> = CMPLT_U %vreg27, %vreg6, pred:%noreg; PredRegs:%vreg17 IntRegs:%vreg27,%vreg6 dbg:../src/getbits.c:53:3 464B ADJCALLSTACKDOWN 0, pred:%noreg, %SP<imp-def>, %SP<imp-use> 480B CALL <ga:@CGA_kernel_advance>, 0, 0, pred:%noreg, 0, %noreg, %P0<imp-def>, %P1<imp-...

On Jul 8, 2012, at 3:42 PM, Sergei Larin <slarin at codeaurora.org> wrote: > ********** EXPANDING POST-RA PSEUDO INSTRS ********** > ********** Function: main > real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, > %D7<imp-def> > replaced by: %R15<def> = TFR %R4, %D7<imp-def> > > The R4 is a subreg of D2 double

...> allowed in all instructions where it is now used. > > For example, by joining %vreg4, %vreg7 and %vreg9 the following code > > %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 > %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 > %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 > > is turned into > > %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17 > aN32_0_7:%vreg4 > > The load instruction however, can only use registers from the rN class, > but the coales...

...8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tba...

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

Hello everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def> replaced by:

...re should be a bug somewhere else. > It seems the PhiElim is working correctly, the output of --debug-only=regalloc shows that %vreg48 is a phi-join register, and intervals looks correct to me : ********** COMPUTING LIVE INTERVALS ********** ********** Function: main BB#0:# derived from  16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17 register: %vreg17 +[16r,352r:0) 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 register: %vreg16 +[32r,240r:0) 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 register: %vreg15 +[48r,160r:0) 64B%vreg14...

...> > It seems the PhiElim is working correctly, the output of --debug-only=regalloc > shows that %vreg48 is a phi-join register, and intervals looks correct to me : > > ********** COMPUTING LIVE INTERVALS ********** > ********** Function: main > BB#0:# derived from  > 16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17 > register: %vreg17 +[16r,352r:0) > 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 > register: %vreg16 +[32r,240r:0) > 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 > register: %vreg15...

...WIN_ALLOCA %EAX<imp-def,dead>, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> %vreg198<def> = COPY %ESP; GR32:%vreg198 MOVSDmr %vreg198, 1, %noreg, 56, %noreg, %vreg194; mem:ST8[%116+56] GR32:%vreg198 FR64:%vreg194 MOVSDmr %vreg198, 1, %noreg, 64, %noreg, %vreg17; mem:ST8[%116+64] GR32:%vreg198 FR64:%vreg17 MOVSDmr %vreg198, 1, %noreg, 48, %noreg, %vreg192; mem:ST8[%116+48] GR32:%vreg198 FR64:%vreg192 MOVSDmr %vreg198, 1, %noreg, 32, %noreg, %vreg191; mem:ST8[%116+32] GR32:%vreg198 FR64:%vreg191 MOVSDmr %vreg198, 1, %noreg, 24, %noreg, %vreg36; mem:ST8[%11...

...my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0,...

...st three >> instructions. I will pick and choose debug output to keep this small. >> >> SelectionDAG has 36 nodes: >> t0: ch = EntryToken >> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 >> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6, t9 >> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 >> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 >...

...<imp-def,dead>, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> > %vreg198<def> = COPY %ESP; GR32:%vreg198 > MOVSDmr %vreg198, 1, %noreg, 56, %noreg, %vreg194; mem:ST8[%116+56] GR32:%vreg198 FR64:%vreg194 > MOVSDmr %vreg198, 1, %noreg, 64, %noreg, %vreg17; mem:ST8[%116+64] GR32:%vreg198 FR64:%vreg17 > MOVSDmr %vreg198, 1, %noreg, 48, %noreg, %vreg192; mem:ST8[%116+48] GR32:%vreg198 FR64:%vreg192 > MOVSDmr %vreg198, 1, %noreg, 32, %noreg, %vreg191; mem:ST8[%116+32] GR32:%vreg198 FR64:%vreg191 > MOVSDmr %vreg198, 1, %noreg, 24, %noreg, %vr...