Displaying 3 results from an estimated 3 matches for "vreg122".
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2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
...)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02
...
queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r
queuing new interval: %vreg122 [68r,400B:0)[400B,688r:1)[688r,752B:2)[752B,1264r:1)[1264r,1312r:3)[1312r,1472B:4)[1472B,1520r:5)[1520r,1764r:6)[2936r,2960B:7)[2980r,2988B:8)[2988B,3024B:9)[3024B,3488B:10) 0 at 68r 1 at 400B-phi 2 at 688r 3 at 1264r 4 at 1312r 5 at 1472B-phi 6 at 1520r 7 at 2936r 8 at 2980r 9 at 2988B-phi 10 at...
2014 Dec 09
2
[LLVMdev] InlineSpiller.cpp bug?
...4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02
>> …
>> queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r
>> queuing new interval: %vreg122 [68r,400B:0)[400B,688r:1)[688r,752B:2)[752B,1264r:1)[1264r,1312r:3)[1312r,1472B:4)[1472B,1520r:5)[1520r,1764r:6)[2936r,2960B:7)[2980r,2988B:8)[2988B,3024B:9)[3024B,3488B:10) 0 at 68r 1 at 400B-phi 2 at 688r 3 at 1264r 4 at 1312r 5 at 1472B-phi 6 at 1520r 7 at 2936r 8 at 2980r 9 at 2988B-phi 10 at...
2014 Nov 21
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin,
I have tried to find a test case for an official target, but failed. It seems to be a rare case.
To do it, I added the 'else' clause in the following:
...
if (VNI->def == OrigVNI->def) {
DEBUG(dbgs() << "orig phi value\n");
SVI->second.DefByOrigPHI = true;
SVI->second.AllDefsAreReloads = false;
propagateSiblingValue(SVI);
continue;