Displaying 20 results from an estimated 25 matches for "vreg12".
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2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
<BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
%vreg5<def> = LDtoc <ga:@a>, %X2; G8RC:%vreg5
%vreg6<def> = LWZ 0, %vreg5; mem:Volatile LD4[@a](tbaa=!"int")
GPRC:%vreg6 G8RC:%vreg5
%vreg7<def> = ADD4 %vreg6<kill>,...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13, <BB#1>; CTRRC8:%vreg13
> B <BB#2>
> Successors according to C...
2016 Feb 20
2
[VSXFMAMutate] OldFMAReg may be wrongly rewritten
...oat %tmp, 0x401F25E360000000
%tmp2 = fadd float %tmp1, 0x3FC1A7B960000000
%tmp3 = select i1 undef, float 0x401F25E360000000, float %tmp2
store float %tmp3, float* undef
br label %loop_bb
}
The code above is triggering a assertion failure when adjusting the live
intervals, since OldFMAReg (%vreg12 in debug info) is actually defined in
two blocks.
I wonder if we can fix this by making the transformation simpler, that is,
instead of doing:
%vreg12<def> = COPY %vreg7; VSSRC:%vreg12,%vreg7
%vreg12<def,tied1> = XSMADDASP %vreg12<tied0>, %vreg0, %vreg4;
VSSRC:%vreg12,%vr...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
Hi,
below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
It worked with llvm 3.1, I don't know if there was a requirement...
2012 May 09
2
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
Hi,
Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
%vreg9<def> = IMPLICIT_DEF
%vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10<def> = IMPLICIT_DEF
%vreg10:hi<def> = COPY %vreg1<kill>
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10:hi<def,read-undef>...
2012 May 09
0
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
...as.paulsson at ericsson.com> wrote:
> Hi,
>
> Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
>
> %vreg9<def> = IMPLICIT_DEF
> %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
> =>
> %vreg10<def> = IMPLICIT_DEF
> %vreg10:hi<def> = COPY %vreg1<kill>
> %vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
> =>
> %vr...
2017 Oct 25
3
How vregs are assigned to operands in IR
...ad i32, i32* %z, align 4
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18
x i8], [18 x i8]* @.str, i32 0, i32 0), i32 %2)
ret i32 0
}
Generated machine instructions (initial)
BB#0: derived from LLVM BB %entry
%vreg11<def> = MOVi32imm 6; GPR32:%vreg11
%vreg12<def> = MOVi32imm 5; GPR32:%vreg12
STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
STRWui %vreg12, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg12
STRWui %vreg11, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg11
.................................
Best
Nisal
2012 May 14
1
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
...AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote:
Hi,
Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
%vreg9<def> = IMPLICIT_DEF
%vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10<def> = IMPLICIT_DEF
%vreg10:hi<def> = COPY %vreg1<kill>
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10:hi<def,read-unde...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...ile the read
%vreg0 has register class "aNlh_0_7". "rN" and "aNlh_0_7" are disjoint.
Is such a PHI node ok?
If it is, then there is a bug in TailDuplication.
Before TailDuplication we have:
BB#2: derived from LLVM BB %bb2
Predecessors according to CFG: BB#1
%vreg12<def> = mv16Sym <ga:@a>; rN:%vreg12
%vreg13<def> = mv_nimm6_ar16 0; aNlh_rN:%vreg13
mv_ar16_r16_rmod1 %vreg13<kill>, %vreg12<kill>; aNlh_rN:%vreg13 rN:%vreg12
brr_uncond <BB#4>;
Successors according to CFG: BB#4(?%)
BB#4: derived from LLVM BB %bb4
Pr...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Thu, 7 Jun 2012 22:14:00 -0700
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
>
> > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> > Predecessors according to CFG: BB#0 BB#1
> > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
> > <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 %vreg13<def> = COPY
> > %vreg12<kill>; CTRRC8:%vreg13,%vreg12 %vreg13<def> = BDNZ8 %vreg13,
> > <BB#1>; CTRRC8:%vreg13 B <BB#2>
> > Succe...
2017 Feb 09
2
Improving the split heuristics for the Greedy Register Allocator
...STACKUP 96, 0, %R1<imp-def,dead>, %R1<imp-use>
> 34 %vreg11<def> = COPY %X3; G8RC:%vreg11 35 Successors
> according to CFG: BB#3(?%)
> 36
> 37 BB#3: derived from LLVM BB %return
> 38 Predecessors according to CFG: BB#1 BB#2 BB#4
> 39 %vreg12<def> = EXTSW_32_64 %vreg11:sub_32; G8RC:%vreg12,%vreg11
> 40 %X3<def> = COPY %vreg12; G8RC:%vreg12
> 41 BLR8 %LR8<imp-use>, %RM<imp-use>, %X3<imp-use>
>
> No matter what I do, vreg15 will get a Callee-Saved Register assigned to
> it. Ho...
2017 Jan 13
2
Improving the split heuristics for the Greedy Register Allocator
...mp-def>
33 ADJCALLSTACKUP 96, 0, %R1<imp-def,dead>, %R1<imp-use>
34 %vreg11<def> = COPY %X3; G8RC:%vreg11 35 Successors
according to CFG: BB#3(?%)
36
37 BB#3: derived from LLVM BB %return
38 Predecessors according to CFG: BB#1 BB#2 BB#4
39 %vreg12<def> = EXTSW_32_64 %vreg11:sub_32; G8RC:%vreg12,%vreg11
40 %X3<def> = COPY %vreg12; G8RC:%vreg12
41 BLR8 %LR8<imp-use>, %RM<imp-use>, %X3<imp-use>
No matter what I do, vreg15 will get a Callee-Saved Register assigned to
it. However, this is suboptima...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg20<def> = LD 40, %vreg1;
mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1
424B %vreg4<def> = DIVD %vreg2, %vreg3;
G8RC:%vreg4,%vreg2,%vreg3
432B %vreg9<def> = DIVD %vreg7, %vreg8;
G8RC:%vreg9,%vreg7,%vreg8
440B %vreg12<def> = DIVD %vreg10, %vreg11;
G8RC:%vreg12,%vreg10,%vreg11
448B %vreg15<def> = DIVD %vreg13, %vreg14;
G8RC:%vreg15,%vreg13,%vreg14
456B %vreg18<def> = DIVD %vreg16, %vreg17;
G8RC:%vreg18,%vreg16,%vreg17
464B %vreg21<def> = DIVD %vreg19, %v...
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
...on, and the assertion I get on the latest trunk (r164162) differs from what I got on r161643 (where it was the PHIelimination that failed). From the log, I have the impression that the assertion is raised on a dead instruction during the spill weight calculation. The dead instruction (definition of vreg12 in the log below) is an instruction I add during if-conversion for use in a later pass. Previously, such dead instructions did not cause any problem...
>
> Any idea what might be going wrong here? I've noticed that there is now something like a flag that needs to be set by code transform...
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...on, and the assertion I get on the latest trunk (r164162) differs from what I got on r161643 (where it was the PHIelimination that failed). From the log, I have the impression that the assertion is raised on a dead instruction during the spill weight calculation. The dead instruction (definition of vreg12 in the log below) is an instruction I add during if-conversion for use in a later pass. Previously, such dead instructions did not cause any problem...
Any idea what might be going wrong here? I've noticed that there is now something like a flag that needs to be set by code transformations tha...
2016 Oct 29
1
Problems with Inline ASM expressions generated in the back end
...e to generate an
Inline ASM expression) I get this error at compilation (at scheduling):
BB#0: derived from LLVM BB %entry
Live Ins: %R1 %R2
%vreg6<def> = COPY %R2; GPR:%vreg6
%vreg5<def> = COPY %R1; GPR:%vreg5
%vreg12<def> = VLOAD_D_WO_IMM; MSA128D:%vreg12 dbg:IfVectorize.c:39:5
INLINEASM <es: (Param1 - Param2); // MSA_I10> [sideeffect]
[attdialect], <llc: /llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X,
Y*>::ret_type llvm::cast(Y*) [with X = llvm...
2013 Oct 22
1
[LLVMdev] System call miscompilation using the fast register allocator
...%RDX<imp-def>
%vreg10<def> = COPY %RDX; GR64:%vreg10
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %R10<imp-def>
%vreg11<def> = COPY %R10; GR64:%vreg11
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %R8<imp-def>
%vreg12<def> = COPY %R8; GR64:%vreg12
%RDI<def> = COPY %vreg8; GR64:%vreg8
%RSI<def> = COPY %vreg9; GR64:%vreg9
%RDX<def> = COPY %vreg10; GR64:%vreg10
%R10<def> = COPY %vreg11; GR64:%vreg11
%R8<def> = COPY %vreg12; GR64:%vreg12
INLINEASM <...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...t; = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1
>> 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:%vreg4,%vreg2,%vreg3
>> 432B %vreg9<def> = DIVD %vreg7, %vreg8; G8RC:%vreg9,%vreg7,%vreg8
>> 440B %vreg12<def> = DIVD %vreg10, %vreg11; G8RC:%vreg12,%vreg10,%vreg11
>> 448B %vreg15<def> = DIVD %vreg13, %vreg14; G8RC:%vreg15,%vreg13,%vreg14
>> 456B %vreg18<def> = DIVD %vreg16, %vreg17; G8RC:%vreg18,%vreg16,%vreg17
>> 464B %vreg21<de...
2012 Oct 20
0
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
On Oct 20, 2012, at 1:23 PM, Vincent Lejeune <vljn at ovi.com> wrote:
> below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
> The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
>
> I don't know if it's a bug of the pass, or if my backend should do something specific before calling the pass.
> It worked with llvm 3.1, I don't know if there wa...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...pVectorize/25_GOOD_map/NEW/6/1/NEW/STDerr3_wo_getSetCCResultType)
Initial selection DAG: BB#15 'foo:vector.ph'
SelectionDAG has 41 nodes:
t0: ch = EntryToken
t4: i32 = Constant<0>
t3: i64,ch = CopyFromReg t0, Register:i64 %vreg12
t6: v8i64 = insert_vector_elt undef:v8i64, t3, Constant:i64<0>
t7: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t6, undef:v8i64
t15: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<1>,
Constant:i64<2>, Constant:...