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Hi, I am writing an analysis pass for a custom processor. I get an unusual situation where the code generated for a BB is BB#23: derived from LLVM BB %sw.bb99 Live Ins: %vr2 %vr0 %vr1 %vr9 %vr3 %vr8 %vr4 %vr5 %vr6 Predecessors according to CFG: BB#22 %vr46<def> = LD_Iri %LV, -4; mem:LD4[FixedStack0] %vr7<def> = ADDri %vr9, 1 %vr47<def> = ADDri %vr46, -4 ST_Iri %LV, -4, %vr47<kill>; mem:ST4[%cpArg.addr] >>> %vr48...

...use any of the code generator components). If it does, making > use of the code generator infrastructure would make sense. > > -Chris > Sample from SUIF disassembler (done by someone else): lda $vr10.p32 <- main.A cvt $vr11.p32 <- $vr10.p32 add $vr12.p32 <- $vr11.p32,$vr9.s32 lod $vr13.s32 <- 0($vr12.p32) cvt $vr8.s32 <- $vr13.s32 mul $vr6.s32 <- $vr7.s32,$vr8.s32 ldc $vr15.s32 <- 5 ldc $vr18.s32 <- 1 add $vr17.s32 <- main.i,$vr18.s32 ******************** So I guess it is RISK. Lots of virtual registers, so I guess allocation isn't a b...

On Tue, 18 Jan 2005, John Cortes wrote: >> Can you say a little bit about MACH-SUIF? With a brief google search, I >> didn't turn up anything that described the architecture. Is it a RISC-like >> machine with 32-bit instruction words? >> > > It's another VM representation. I haven't really gotten to know the nitty > gritty of the language so

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;