search for: vk128opnd

...::v128i16); return false; }]>; foreach RegId = 0-31 in def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence "Mask%u", 0, 31)>; def VK128Opnd : RegisterOperand<VK128> { let ParserMatchClass = MSA128AsmOperand; } class LD_INDIRECT_DESC_BASE2<string instr_asm, ValueType TyNode, RegisterOperand ROWD, RegisterOperand ROWSI = ROWD, R...

...lass LD_INDIRECT_DESC_BASE2<string instr_asm, RegisterOperand ROWD, RegisterOperand ROWSP = ROWD, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm); dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx256xmem:$wsi); string AsmString = !strconcat("$wd = LS[$wsi]; // iread (or Mips MSA's LD) strinstr_asm = ", instr_asm); list<dag> Pattern = [(...

..._DESC_BASE2<string instr_asm, > RegisterOperand ROWD, > RegisterOperand ROWSP = ROWD, > InstrItinClass itin = NoItinerary> { > dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm); > dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx256xmem:$wsi); > string AsmString = !strconcat("$wd = LS[$wsi]; // iread (or Mips MSA's LD) > strinstr_asm = ", > instr_asm); > list<...

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition.

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it