Displaying 4 results from an estimated 4 matches for "vgpr0".
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vgpr1
2020 Nov 19
1
Problems with undef subranges in identity copies
.... The fundamental problem is complexity from the fact that undef
values are a special case since they don't have an associated
VNInfo/Segment unless the value is used across blocks.
For example, in this case, %0 has 2 subregisters sub0 and sub1:
bb.0:
undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1:
%0:vreg_64 = COPY %0
S_CBRANCH_EXECNZ %bb.1, implicit $exec
bb.2:
undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 killed %0.sub1, implicit $mode, implicit $exec
S_BRANCH %bb.1
sub0 has no defined values anywhere in this function. The value only
exists due to this iden...
2013 Oct 10
2
[LLVMdev] [PATCH] R600/SI: Embed disassembly in ELF object
...bugging in Mesa clients.
Here's an example of the output in a Mesa client with a corresponding
patch and RADEON_DUMP_SHADERS set:
Shader Disassembly:
S_WQM_B64 EXEC, EXEC ; BEFE0A7E
S_MOV_B32 M0, SGPR6 ; BEFC0306
V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302
V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202
V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102
V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002
EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F 00010203
S_ENDPGM...
2012 Oct 26
0
[LLVMdev] Data sharing between two ALUs and avoiding illegal copies
...d VGPRs for vALU.
The vALU can read from VGPRs and also SGPRs, but the sALU can only read
from SGPRs. This restriction on the sALU seems to be causing the
instruction selector to generate some illegal copies, which is the main
problem I'm trying to solve. For example:
NODE0 = ISD::ADD SGPR0, VGPR0
can be selected to:
SGPR2 = COPY VGPR0
SGPR1 = S_ADD SGPR0, SGPR2
This leaves us with a copy from a VGPR to an SGPR, which is illegal.
Any suggestions on how to solve this problem or how best to model these
two ALUs?
Thanks,
Tom
2013 Oct 10
0
[LLVMdev] [PATCH] R600/SI: Embed disassembly in ELF object
...s an example of the output in a Mesa client with a corresponding
> patch and RADEON_DUMP_SHADERS set:
>
> Shader Disassembly:
>
> S_WQM_B64 EXEC, EXEC ; BEFE0A7E
> S_MOV_B32 M0, SGPR6 ; BEFC0306
> V_INTERP_MOV_F32 VGPR0, P0, 3, 0, [M0] ; C8020302
> V_INTERP_MOV_F32 VGPR1, P0, 2, 0, [M0] ; C8060202
> V_INTERP_MOV_F32 VGPR2, P0, 1, 0, [M0] ; C80A0102
> V_INTERP_MOV_F32 VGPR3, P0, 0, 0, [M0] ; C80E0002
> EXP 15, 0, 0, 1, 1, VGPR3, VGPR2, VGPR1, VGPR0 ; F800180F...