Displaying 5 results from an estimated 5 matches for "vextractf128_shuffle_mask".
2009 Dec 03
2
[LLVMdev] Duplicate Label in Generates ISel
...ere
This seems to happen because of a pattern I added for VEXTRACTF128 which uses
extract_subreg:
[(set DSTREGCLASS:$dst,
(DSTTYPE (extract_subreg
(vector_shuffle
(SRCTYPE undef),
(SRCTYPE SRCREGCLASS:$src1),
VEXTRACTF128_shuffle_mask:$src2),
x86_subreg_128bit)))],
def x86_subreg_128bit : PatLeaf<(i32 1)>;
Curiously, I have analogous patterns for VINSERTF128 that use insert_subreg
but it doesn't generate any duplicate case values.
Anyone seen something like this before? Any ideas on how to fix i...
2009 Dec 03
0
[LLVMdev] Duplicate Label in Generates ISel
...a pattern I added for VEXTRACTF128 which
> uses extract_subreg:
>
> [(set DSTREGCLASS:$dst,
> (DSTTYPE (extract_subreg
> (vector_shuffle
> (SRCTYPE undef),
> (SRCTYPE SRCREGCLASS:$src1),
> VEXTRACTF128_shuffle_mask:$src2),
> x86_subreg_128bit)))],
>
> def x86_subreg_128bit : PatLeaf<(i32 1)>;
Whoops, I forgot to fill in types:
(outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2)
[(set DSTREGCLASS:$dst,
(v4f32 (extract_subreg
(vector_shuffle...
2009 Dec 03
1
[LLVMdev] Duplicate Label in Generates ISel
...in types:
>
> (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2)
>
> [(set DSTREGCLASS:$dst,
> (v4f32 (extract_subreg
> (vector_shuffle
> (v8f32 undef),
> (v8f32 SRCREGCLASS:$src1),
> VEXTRACTF128_shuffle_mask:$src2),
> x86_subreg_128bit)))],
Well, it's conflicting with the hard-coded case statement from
DAGISelEmitter.cpp. What's the best way to resolve this? Introduce
another DAG operator that means the same thing as ISD::EXTRACT_SUBREG
but that can be used as the top-le...
2009 Dec 02
5
[LLVMdev] Selecting Vector Shuffle of Different Types
...MRMDestMem, "extractf128", undef, X86f32, X86i32i8,
// rr
[(set VR128:$dst,
(v4f32 (vector_shuffle
(v8f32 undef), (v8f32 VR256:$src1),
VEXTRACTF128_shuffle_mask:$src2)))]>;
(This is simplified for the sake of exposition but this gets the idea across).
TableGen reports a type contradition:
VEXTRACTF128_256mri: (st:isVoid (vector_shuffle:v4f32 (undef:v8f32),
VR256:v8f32:$src1, (build_vector)<<P:Predicate_VEXTRACTF128_shuffle_mask>>:
$src2...
2009 Dec 03
0
[LLVMdev] Selecting Vector Shuffle of Different Types
...MDestMem, "extractf128", undef, X86f32, X86i32i8,
> // rr
> [(set VR128:$dst,
> (v4f32 (vector_shuffle
> (v8f32 undef), (v8f32 VR256:$src1),
> VEXTRACTF128_shuffle_mask:$src2)))]>;
>
> (This is simplified for the sake of exposition but this gets the idea across).
>
> TableGen reports a type contradition:
>
> VEXTRACTF128_256mri: (st:isVoid (vector_shuffle:v4f32 (undef:v8f32),
> VR256:v8f32:$src1, (build_vector)<<P:Predicate_VEXTRAC...