Displaying 3 results from an estimated 3 matches for "vex_lig".
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venlig
2013 May 20
2
[LLVMdev] VCOMISS instruction in X86
...alar and packed instructions in X86.
The instruction VCOMISS is scalar. May I remove SSEPackedSingle/SSEPackedDouble domain from it?
defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
VEX_LIG;
let Pattern = []<dag> in {
defm VCOMISS : sse12_ord_cmp<0x2F, VR128,...
2018 Mar 28
0
x86 instruction format which takes a single 64-bit immediate
...PS
TAPD - Set map to TA and prefix to PD
TAXD - Set map to TA and prefix to XD
VEX - Set encoding to VEX.
VEX_W - Set VEX_WPrefix to VEX.W=1
VEX_WIG - VEX_WPrefix to VEX.W ignore value.
VEX_4V - Set hasVEX_4V=1. Implies VEX.
VEX_L - set hasVEX_L=1
VEX_LIG - Set ignoresVEX_L
EVEX - Set encoding to EVEX.
EVEX_4V - Set hasVEX_4V=1. Implies EVEX.
EVEX_K - Set hasEVEX_K=1.
EVEX_KZ - Set hasEVEX_Z=1. Implies EVEX_K.
EVEX_B - Set hasEVEX_B=1
EVEX_RC - Set hasEVEX_RC=1
EVEX_V512 - Sets has_EVEX_L2=1; hasVEX_L=0;
EV...
2018 Mar 28
4
x86 instruction format which takes a single 64-bit immediate
I am attempting to create an instruction which takes a single 64-bit
immediate. This doesn't seem like a thing that would exist already (because
who needs an instruction which just takes an immediate?) How might I
implement this easily? Perhaps I could use a format which encodes a
register, which is then unused?
Thanks for the help.
Gus
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