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Hello everybody I am trying to connect my asterisk to a payment equipment trough PSTN. I have a TDM400P card with an fxs module an the equipment use modem to send data! I was thinking to implement a software data modem in asterisk, but I found out that there is just faxmodem for asterisk, Is anyone here know something about software data modem working with asterisk to help out? Thanks,

I am adding code in Xen that printk''s a size_t and find that I can''t write code (short of ifdef''ing) that compiles on both 32-bit and 64-bit because size_t is typedef''d in Xen as an unsigned long. C.f. http://www.velocityreviews.com/forums/t438359-portable-way-to-printf-a-sizet-instance.html It appears that the %z format is understood by Xen printk. Is the typedef historical and should be removed? Or is it necessary for some (older?) compilers? If it is not going to be removed, is there a workaround (other than ifdef&...

...olics Processor Designer, I tried to find that in google, but I am not sure that I found what you were speaking about. Do you have a link ? I just discover that this mailing list is for speaking about LLVM developpement and usage only, so for all non LLVM related discussions, go to http://www.velocityreviews.com/forums/t964068-reflexions-about-a-new-hdl-language.html. Cheers, Jonas

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is

Hi everybody, I use for the moment "#" at the begining of each line for comments. Is there any possibility to comment more than one line, like something which shows the beggingng and the end of the comment? Or is there a possibility to comment only a part of a line? Thanks, Mihai [[alternative HTML version deleted]]

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never