search for: vc2

I have two matrix with same dimensions. I want to do t.test using each column from 2 different matrix. Row n Column names in both matrix are same. e.g. Matrix1 id VC1 VC2 VC3 R 1 2 3 R1 4 5 6 R3 7 8 9 Matrix2 id VC1 VC2 VC3 R 10 11 12 R1 13 14 15 R3 16 17 18 want to do t.test using each column (with same name ) using Matrix1 and Matrix2 for eg t.test(Matrix1$VC1, Matrix2$VC1)$p.value What is the best way to do it. I have dataset...

I have two matrix with same dimensions. I want to do t.test using each column from 2 different matrix. Column names in both matrix are same. e.g. Matrix1 id VC1 VC2 VC3 R 1 2 3 R1 4 5 6 R3 7 8 9 Matrix2 id VC1 VC2 VC3 R 10 11 12 R1 13 14 15 R3 16 17 18 want to do t.test for eg t.test(Matrix1$VC1, Matrix2$VC1)$p.value What is the best way to do it. I have dataset with 4000 columns for each matrix with same row and column names. Thanks a l...

Hi Renato, Thanks for your response. My concern was actually this. For example, take vector type V8i16 on X86 target With llvm.sad() intrinsic: VC1 (Vector Cost) = Cost associated with "PSAD" instruction. W/ llvm.absd() and llvm.hadd() VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? ) As I will be querying with getIntrinsicCost(ID) for these two intrinsics separately, Will VC1==VC2? May be I am missing something obvious? Regards, Shahid > -----Original Message----- > From: Renato Go...

On 4 May 2015 at 08:37, Shahid, Asghar-ahmad <Asghar-ahmad.Shahid at amd.com> wrote: > My worry is regarding the query for cost calculation for specific SAD > instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer. Hi Shahid, The vectorizer's cost model has the ability to return different costs for the same instruction based on the arguments (scalar/vector,

...ard[guardsize]; \ + char NMI_stack[EXCEPTION_STKSZ]; \ + char DB_stack_guard[guardsize]; \ + char DB_stack[EXCEPTION_STKSZ]; \ + char MCE_stack_guard[guardsize]; \ + char MCE_stack[EXCEPTION_STKSZ]; \ + char VC_stack_guard[guardsize]; \ + char VC_stack[optional_stack_size]; \ + char VC2_stack_guard[guardsize]; \ + char VC2_stack[optional_stack_size]; \ + char IST_top_guard[guardsize]; \ /* The exception stacks' physical storage. No guard pages required */ struct exception_stacks { - ESTACKS_MEMBERS(0) + ESTACKS_MEMBERS(0, 0) }; /* The effective cpu entry area map...

...cado_6ae2tn_f/serial-vc1-20191223-061943-73qpR3NF,server,nowait > \ > -device virtio-serial-pci,id=virtio_serial_pci0,bus=pci.0,addr=0x3 \ > -device > virtserialport,id=vc1,name=vc1,chardev=chardev_vc1,bus=virtio_serial_pci0.0,nr=1 > \ > -chardev > socket,id=chardev_vc2,path=/var/tmp/avocado_6ae2tn_f/serial-vc2-20191223-061943-73qpR3NF,server,nowait > \ > -device virtio-serial-pci,id=virtio_serial_pci1,bus=pci.0,addr=0x4 \ > -device > virtconsole,id=vc2,name=vc2,chardev=chardev_vc2,bus=virtio_serial_pci1.0,nr=1 > \ > -chardev > so...

...r back to the stack in the IRET frame if > + * entered from kernel-mode. > + * > + * If entered from kernel-mode the return stack is validated first, and if it is > + * not safe to use (e.g. because it points to the entry stack) the #VC handler > + * will switch to a fall-back stack (VC2) and call a special handler function. > + * > + * The macro is only used for one vector, but it is planned to extend it in the ^^^^^^^^^^^ "... to be extended..." ... > @@ -674,6 +675,56 @@ asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) &...

...SYSCALL entry path it switches to the task stack, if entered from kernel-mode it tries to switch back to the previous stack in the IRET frame. The stack found in the IRET frame is validated first, and if it is not safe to use it for the #VC handler, the code will switch to a fall-back stack (the #VC2 IST stack). From there it can cause nested exceptions again. Signed-off-by: Joerg Roedel <jroedel at suse.de> Link: https://lore.kernel.org/r/20200724160336.5435-48-joro at 8bytes.org --- arch/x86/entry/entry_64.S | 78 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/idtentry.h...

...1]),mean)) re1p <- 1- m*sum(me1*(1-me1))/(k*(m-1)*mean(me1)*(1-mean(me1))) ve1m <- ve1*(1+(m-1)*re1)/(k*m) ## CONTROL ## r2 <- cor(d2[,2:3])[1,2] # COST # ac2 <- anova(lm(c~g,d2)) rc2 <- (ac2[1,3]-ac2[2,3])/(ac2[1,3]+(m-1)*ac2[2,3]) if (rc2 < 0) rc2 <- 0 vc2 <- var(d2[,2]) mc2 <- as.vector(by(d2[,2],as.numeric(d2[,1]),mean)) vc2m <- vc2*(1+(m-1)*rc2)/(k*m) # EFECT # ae2 <- anova(lm(e~g,d2)) re2 <- (ae2[1,3]-ae2[2,3])/(ae2[1,3]+(m-1)*ae2[2,3]) if (re2 < 0) re2 <- 0 ve2 <- var(d2[,3]) me2 <- as.vector(...

...d intrinsics > > On 5 May 2015 at 15:41, Shahid, Asghar-ahmad <Asghar- > ahmad.Shahid at amd.com> wrote: > > With llvm.sad() intrinsic: > > VC1 (Vector Cost) = Cost associated with "PSAD" instruction. > > > > W/ llvm.absd() and llvm.hadd() > > VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? > > ) > > > > As I will be querying with getIntrinsicCost(ID) for these two intrinsics > separately, Will VC1==VC2? > > I see. You are correct to say that this is a crude approximation....

.... With Secure Nested Paging (SNP), which needs additional enablement, a #VC can happen on any memory access. I wrote the IST handling entry code for #VC with that in mind, but do not actually enable it. This is the reason why the #VC handler just panics the system when it ends up on the fall-back (VC2) stack, with SNP enabled it needs to handle the SNP exit-codes in that path. Regards, Joerg

.... With Secure Nested Paging (SNP), which needs additional enablement, a #VC can happen on any memory access. I wrote the IST handling entry code for #VC with that in mind, but do not actually enable it. This is the reason why the #VC handler just panics the system when it ends up on the fall-back (VC2) stack, with SNP enabled it needs to handle the SNP exit-codes in that path. Regards, Joerg

...d Paging (SNP), which needs additional enablement, a #VC can > happen on any memory access. I wrote the IST handling entry code for #VC > with that in mind, but do not actually enable it. This is the reason why > the #VC handler just panics the system when it ends up on the fall-back > (VC2) stack, with SNP enabled it needs to handle the SNP exit-codes in > that path. And recursive #VC was instant death, right? Because there's no way to avoid IST stack corruption in that case.

...diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index c49cf594714b..5a85730eb0ca 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c @@ -85,7 +85,7 @@ struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = { EPAGERANGE(VC2), }; -static bool in_exception_stack(unsigned long *stack, struct stack_info *info) +static bool __always_inline in_exception_stack(unsigned long *stack, struct stack_info *info) { unsigned long begin, end, stk = (unsigned long)stack; const struct estack_pages *ep; @@ -126,7 +126,7 @@ stati...

-----Original Message----- From: Richard W.M. Jones [mailto:rjones@redhat.com] Sent: Friday, January 17, 2014 4:40 PM To: Исаев Виталий Анатольевич Cc: libguestfs@redhat.com Subject: Re: [Libguestfs] LVM mounting issue On Fri, Jan 17, 2014 at 09:45:34AM +0000, Исаев Виталий Анатольевич wrote: > Be sure, that “unknown device” was not written by me :) > > I use libguestfs 1.16.34:

...lue continue to the next column Once again thx for help. sata pinal wrote: > > I have two matrix with same dimensions. I want to do t.test using each > column from 2 different matrix. > Row n Column names in both matrix are same. > > e.g. > Matrix1 > id VC1 VC2 VC3 > R 1 2 3 > R1 4 5 6 > R3 7 8 9 > > > Matrix2 > id VC1 VC2 VC3 > R 10 11 12 > R1 13 14 15 > R3 16 17 18 > > want to do t.test using each column (with same name ) using Matrix1 and > Matrix2 > > for eg t.test(Matrix1$VC...

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or