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2014 Sep 30
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
Wow. Somehow, I forgot about vbroadcast and vpbroadcast. =[ Sorry about that. I'll fix those. On Fri, Sep 26, 2014 at 3:39 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > Here is another test. > > When looking at the AVX codegen, I noticed that, when using the new > shuffle low...
2014 Sep 23
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
On Tue, Sep 23, 2014 at 2:35 PM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > If you don’t want to spend time on this, I’d be happy to create a > candidate patch for review? I’ve been unclear if you were taking patches > for your shuffle work prior to it becoming the default. While I'm happy to work on it, I'm even more happy to have patches. =D -------------- next
2017 Aug 06
2
VBROADCAST Implementation Issues
...gt;> >>>>> def BROADCASTR_256B : I<0x21, MRMSrcReg, (outs VR_2048:$dst), (ins >>>>> GR64:$src), >>>>> "BROADCASTR_256B\t{$src, $dst|$dst, $src}", >>>>> [(set VR_2048:$dst, (v64i32 (X86VBroadcast >>>>> GR64:$src)))], >>>>> IIC_MOV_MEM>, TA; >>>>> >>>>> >>>>> >>>>> def: Pat<(v64f32 (X86VBroadcast GR64:$src)), >>>>> (BROADCASTR_256B GR64:$src)>; >>>&g...
2017 Aug 07
2
VBROADCAST Implementation Issues
...> def BROADCASTR_256B : I<0x21, MRMSrcReg, (outs VR_2048:$dst), (ins >>>>>>> GR64:$src), >>>>>>> "BROADCASTR_256B\t{$src, $dst|$dst, $src}", >>>>>>> [(set VR_2048:$dst, (v64i32 (X86VBroadcast >>>>>>> GR64:$src)))], >>>>>>> IIC_MOV_MEM>, TA; >>>>>>> >>>>>>> >>>>>>> >>>>>>> def: Pat<(v64f32 (X86VBroadcast GR64:$src)), >>>>>...
2011 Mar 16
3
[LLVMdev] Long-Term ISel Design
...'t completely understand why but Bruno indicated it was to address inefficiecies. One of those is the need to check masks multiple times (once at legalize and again at isel). 2. Sometimes DAGs are legal in some contexts but not others and it is a pain to deal with. A good example is VBROADCAST, where a <0,0,0,0> shuffle is natively supported if the source vector is in memory. Otherwise it's not legal and manual lowering is required. In this case the legality check is doing the DAG match by hand, replicating what TableGen-produced code already does. These two examp...
2011 Mar 17
0
[LLVMdev] Long-Term ISel Design
...perations. Now instead of forming specific carefully constructed shuffle masks (not making sure other code doesn't violate them) it can just directly form the X86ISD node. > 2. Sometimes DAGs are legal in some contexts but not others and it is a > pain to deal with. A good example is VBROADCAST, where a <0,0,0,0> > shuffle is natively supported if the source vector is in memory. > Otherwise it's not legal and manual lowering is required. In this > case the legality check is doing the DAG match by hand, replicating > what TableGen-produced code already does....
2017 Aug 07
3
VBROADCAST Implementation Issues
...(outs VR_2048:$dst), >>>>>>>>>>> (ins GR64:$src), >>>>>>>>>>> "BROADCASTR_256B\t{$src, $dst|$dst, $src}", >>>>>>>>>>> [(set VR_2048:$dst, (v64i32 (X86VBroadcast >>>>>>>>>>> GR64:$src)))], >>>>>>>>>>> IIC_MOV_MEM>, TA; >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>&...
2011 Mar 17
2
[LLVMdev] Long-Term ISel Design
...ng pre-table-driven-isel passes so we'd still have a chance to do some cleanup before the main table-driven isel. Obviously a lot of details have to be worked out. >> 2. Sometimes DAGs are legal in some contexts but not others and it is a >> pain to deal with. A good example is VBROADCAST, where a <0,0,0,0> >> shuffle is natively supported if the source vector is in memory. >> Otherwise it's not legal and manual lowering is required. In this >> case the legality check is doing the DAG match by hand, replicating >> what TableGen-produced cod...
2011 Mar 18
0
[LLVMdev] Long-Term ISel Design
...shuffles, all of the matching code would end up as C++ code in X86ISelDagToDag, which would give us all of the problems we had before by moving to X86ISD nodes. >>> 2. Sometimes DAGs are legal in some contexts but not others and it is a >>> pain to deal with. A good example is VBROADCAST, where a <0,0,0,0> >>> shuffle is natively supported if the source vector is in memory. >>> Otherwise it's not legal and manual lowering is required. In this >>> case the legality check is doing the DAG match by hand, replicating >>> what TableGen-...
2011 Mar 27
2
[LLVMdev] Long-Term ISel Design
...thing from CSE'ing a load away and "breaking" the dag, or > moving an add between the nodes etc. You're violating a design > principle of selection dags. Fair enough. The current proposal eliminates any need to do any of this. I did end up creating a special X86 node for VBROADCAST because you're right, its too brittle to rely on something else not breaking it. >> But the real point is that in forming the X86ISD node currently, I'm >> doing exaclty what the tblgen-generated code already does. If the >> shuffle doesn't take a memory operand, the...
2014 Sep 10
13
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
On Tue, Sep 9, 2014 at 11:39 PM, Chandler Carruth <chandlerc at google.com> wrote: > Awesome, thanks for all the information! > > See below: > > On Tue, Sep 9, 2014 at 6:13 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: >> >> You have already mentioned how the new shuffle lowering is missing >> some features; for example, you explicitly