search for: valuetyp

Displaying 20 results from an estimated 281 matches for "valuetyp".

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2015 Feb 18
2
[LLVMdev] local variable in Pattern definition?
Hi guys, When I am trying to define pattern in a multi class, I got something like this: “ multi class P_PAT<string sty, SDNode tNode> { def : Pat<( !cast<ValueType>(“v2” # sty) (tNode !cast<ValueType>(“v2” # sty):$src1, !cast<ValueType>(“v2” # sty):$src2) ), ( add !cast<ValueType>(“v2” # sty):$src1, !cast<ValueType>(“v2” # sty):$src2) >; } “ noticed that in the above pattern, the "!cast<ValueType>...
2008 Sep 02
2
[LLVMdev] Instruction MVT::ValueTypes
Is there an easy way to get the MVT::ValueType of a MachineInstruction MachineOperand? For example, the register operand of an x86 MOVAPD should have an MVT::ValueType of v2f64. A MOVAPS register operand should have an MVT::ValueType of v4f32. So given a MachineInstruction and its MachineOperands is there some easy way to derive this infor...
2006 May 13
2
[LLVMdev] TableGen: RegisterClass question
Hi, I'm porting some existing code of mine to CVS HEAD, and don't understand something about new RegisterClass TableGen definition: class RegisterClass<string namespace, list<ValueType> regTypes,........ { ..... string Namespace = namespace; What is this "namespace" thing? It looks like it should contain the name of backend, right? // RegType - Specify the ValueType of the registers in this register // class. Note that all registers in a reg...
2007 Jun 22
3
[LLVMdev] a possible alternative for pre-legalize extended ValueTypes
After doing a bunch of work for moving pre-legalize extended ValueTypes into a table in SelectionDAG, I may have just found a simpler approach. There are under 32 simple ValueType values, so we only really need 5 bits to represent those. ValueType is already a 32-bit type on most hosts; what if we make use of the remaining 27 bits instead of using an external table?...
2008 Jun 05
1
[LLVMdev] Type safe MVT::ValueType
I would like to apply the attached patch which changes MVT::ValueType (currently a uint32_t) into a one-element struct (the element being a uint32_t). This makes it harder to misuse MVT::ValueType. Thanks to this patch I found two cases in which the arguments to DAG.getConstant were inverted and one in which getStore was being passed an ValueType for the "vola...
2008 Sep 02
0
[LLVMdev] Instruction MVT::ValueTypes
On Sep 2, 2008, at 10:42 AM, David Greene wrote: > Is there an easy way to get the MVT::ValueType of a MachineInstruction > MachineOperand? For example, the register operand of an x86 MOVAPD > should > have an MVT::ValueType of v2f64. A MOVAPS register operand should > have an > MVT::ValueType of v4f32. The short answer is no. A op of a number of different VTs can map to...
2007 May 21
1
[LLVMdev] Simplifing the handling of pre-legalize vector nodes
Right now there are special SelectionDAG node kinds for operations on "abstract" vector types (VLOAD, VADD, and all the rest), and a special MVT::Vector ValueType for them. These nodes carry two additional operands, constants which specify the vector length and element type. All of this is only used before legalize; then they are replaced with regular node kinds and value types. It seems that a number of things would be considerably simpler if the pre-lega...
2007 Jun 19
3
[LLVMdev] TargetRegisterClass for Physical Register
On Monday 18 June 2007 19:02, Christopher Lamb wrote: > Take a look at getPhysicalRegisterRegClass( > const MRegisterInfo *MRI, > MVT::ValueType VT, > unsigned reg) > > in ScheduleDAG.cpp. Yuck. I was afraid of that. What is the ValueType needed for? Isn't the register id itself an indication of the ValueType it represents? Where I'm at I don't have access to a ValueType. I understand that a physical re...
2007 Jun 22
0
[LLVMdev] a possible alternative for pre-legalize extended ValueTypes
On Jun 22, 2007, at 11:06 AM, Dan Gohman wrote: > After doing a bunch of work for moving pre-legalize extended > ValueTypes > into a table in SelectionDAG, I may have just found a simpler > approach. > > There are under 32 simple ValueType values, so we only really need > 5 bits > to represent those. ValueType is already a 32-bit type on most > hosts; what > if we make use of the remainin...
2008 Sep 03
3
[LLVMdev] Instruction MVT::ValueTypes
On Tuesday 02 September 2008 16:47, Evan Cheng wrote: > On Sep 2, 2008, at 10:42 AM, David Greene wrote: > > Is there an easy way to get the MVT::ValueType of a MachineInstruction > > MachineOperand? For example, the register operand of an x86 MOVAPD > > should > > have an MVT::ValueType of v2f64. A MOVAPS register operand should > > have an > > MVT::ValueType of v4f32. > > The short answer is no. A op of a numbe...
2009 Aug 18
2
[LLVMdev] gcc4.4's -O2 is breaking include/llvm/CodeGen/ValueTypes.h
I was running into a problem with compiling llvm with gcc 4.4 on fedora 11 with --enable-optimized. I was seeing this warning dozens of times: /net/hakodate/scratch/llvm/llvm/include/llvm/CodeGen/ValueTypes.h: In member function ‘llvm::SDNode*<unnamed>::SPUDAGToDAGISel::Select(llvm::SDValue)’: /net/hakodate/scratch/llvm/llvm/include/llvm/CodeGen/ValueTypes.h:362: warning: comparison always false due to limited range of data type And on "make check" would print out: llc: /scratch/ll...
2006 May 14
0
[LLVMdev] TableGen: RegisterClass question
On Sat, 13 May 2006, Vladimir Prus wrote: > I'm porting some existing code of mine to CVS HEAD, and don't understand > something about new RegisterClass TableGen definition: > > class RegisterClass<string namespace, list<ValueType> regTypes,........ > { > ..... > string Namespace = namespace; > > What is this "namespace" thing? It looks like it should contain the name of > backend, right? Right. This is "X86" "Alpha" "PPC" etc, which is used to pr...
2009 Aug 19
0
[LLVMdev] gcc4.4's -O2 is breaking include/llvm/CodeGen/ValueTypes.h
On Aug 18, 2009, at 11:50 AM, Erick Tryzelaar wrote: > I was running into a problem with compiling llvm with gcc 4.4 on > fedora 11 with --enable-optimized. I was seeing this warning dozens of > times: > > /net/hakodate/scratch/llvm/llvm/include/llvm/CodeGen/ValueTypes.h: In > member function > ‘llvm::SDNode*<unnamed>::SPUDAGToDAGISel::Select(llvm::SDValue)’: > /net/hakodate/scratch/llvm/llvm/include/llvm/CodeGen/ValueTypes.h:362: > warning: comparison always false due to limited range of data type > > And on "make check" would...
2008 Sep 03
0
[LLVMdev] Instruction MVT::ValueTypes
On Sep 3, 2008, at 1:14 PM, David Greene wrote: > On Tuesday 02 September 2008 16:47, Evan Cheng wrote: >> On Sep 2, 2008, at 10:42 AM, David Greene wrote: >>> Is there an easy way to get the MVT::ValueType of a >>> MachineInstruction >>> MachineOperand? For example, the register operand of an x86 MOVAPD >>> should >>> have an MVT::ValueType of v2f64. A MOVAPS register operand should >>> have an >>> MVT::ValueType of v4f32. >> >> T...
2009 Mar 10
1
[LLVMdev] 2.5 Pre-release1 available for testing
...ls to build on ppc64: > > http://koji.fedoraproject.org/koji/taskinfo?taskID=1148023 > > make[1]: Entering directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' > llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td > tblgen: IntrinsicEmitter.cpp:137: void > EmitTypeForValueType(std::ostream&, llvm::MVT::SimpleValueType): > Assertion `false && "Unsupported ValueType!"' failed. > make[1]: Leaving directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' > make[1]: *** [/builddir/build/BUILD/llvm-2.5/lib/VMCore/Release/Intrinsics.gen.tmp]...
2007 Jun 18
2
[LLVMdev] TargetRegisterClass for Physical Register
How do I get the TargetRegisterClass for a physical register? SSARegMap::getRegClass only works for virtual registers. -Dave
2007 Jun 19
0
[LLVMdev] TargetRegisterClass for Physical Register
Take a look at getPhysicalRegisterRegClass( const MRegisterInfo *MRI, MVT::ValueType VT, unsigned reg) in ScheduleDAG.cpp. -- Christopher Lamb On Jun 18, 2007, at 4:52 PM, David A. Greene wrote: > How do I get the TargetRegisterClass for a physical register? > SSARegMap::getRegClass only works for virtual registers. > >...
2007 Jul 14
1
[LLVMdev] [PATCH] fix a "jump to case label crosses initialization of llvm::MVT::ValueType VT" error
...============== --- llvm.orig/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2007-07-14 16:59:23.000000000 +0200 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2007-07-14 16:59:52.000000000 +0200 @@ -696,7 +696,7 @@ } } break; - case ISD::EH_RETURN: + case ISD::EH_RETURN: { MVT::ValueType VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. switch (TLI.getOperationAction(Node->getOpcode(), VT)) { @@ -710,6 +710,7 @@ Result = LegalizeOp(Node->getOperand(0)); break; } + } break; case ISD:...
2014 Jul 17
2
[LLVMdev] Fwd: Re: [PATCH] [TABLEGEN] Do not crash on intrinsics with names longer than 40 characters
...=================================================================== --- llvm/trunk/test/TableGen/intrinsic-long-name.td +++ llvm/trunk/test/TableGen/intrinsic-long-name.td @@ -0,0 +1,32 @@ +// RUN: llvm-tblgen -gen-intrinsic %s | FileCheck %s +// XFAIL: vg_leak + +class IntrinsicProperty; + +class ValueType<int size, int value> { + string Namespace = "MVT"; + int Size = size; + int Value = value; +} + +class LLVMType<ValueType vt> { + ValueType VT = vt; +} + +class Intrinsic<string name, list<LLVMType> param_types = []> { + string LLVMName = name; + bit isTarge...
2008 Jan 30
2
[LLVMdev] no build, no joy
...In file included from /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/ SPUISelDAGToDAG.cpp:334: /Volumes/mrs5/net/llvm/llvm-build/lib/Target/CellSPU/ SPUGenDAGISel.inc: In member function ‘llvm::SDNode* SPUDAGToDAGISel::Emit_5(const llvm::SDOperand&, unsigned int, unsigned int, llvm::MVT::ValueType, llvm::MVT::ValueType)’: /Volumes/mrs5/net/llvm/llvm-build/lib/Target/CellSPU/SPUGenDAGISel.inc: 948: error: ‘Tmp2’ was not declared in this scope make[3]: *** [/Volumes/mrs5/net/llvm/llvm-build/lib/Target/CellSPU/ Debug/SPUISelDAGToDAG.o] Error 1 make[2]: *** [CellSPU/.makeall] Error 2 make[1]:...