Displaying 6 results from an estimated 6 matches for "v512i32".
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v1i32
2018 Jul 24
2
KNL Vectorization with larger vector width
...gt; and rest scalar. so here when i keep iteration=2047 i get all
scalar why is that so? similarly in polly as well i cant see vector mixes
like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it
should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32>
how to do this?
What am i missing here?
what further changes do i need to make?
Please help...
On Tue, Jul 24, 2018 at 1:52 AM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 12:40 PM, hameeza ahmed wrote:
>
>> Thank You. I got it...
2018 Jan 17
3
Does it make sense to upstream some MVT's?
...56i16
20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of
v400):
v512i16
32-bit versions of the above 16-bit registers (to represent 32-bit
accumulators for MAD instructions and also dual-issue "wide" instructions
to the dual non-MAD ALU's in each lane)
v256i32
v512i32
For those interested in more details about Pixel Visual Core, the 6th
edition of Hennessy and Patterson's "Computer Architecture: A Quantitative
Approach" http://a.co/et2K1xk has a section about it (Section 7.7 pg
579-592). I'll bring my copy to the next Bay Area LLVM Social if...
2018 Jul 24
2
KNL Vectorization with larger vector width
...e when i keep iteration=2047 i get all
>> scalar why is that so? similarly in polly as well i cant see vector mixes
>> like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it
>> should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32>
>>
>> how to do this?
>>
>> What am i missing here?
>> what further changes do i need to make?
>>
>> Please help...
>>
>>
>>
>>
>>
>>
>> On Tue, Jul 24, 2018 at 1:52 AM, Friedman, Eli <efri...
2018 Jan 17
0
Does it make sense to upstream some MVT's?
...20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of v400):
v512i16
32-bit versions of the above 16-bit registers (to represent 32-bit accumulators for MAD instructions and also dual-issue "wide" instructions to the dual non-MAD ALU's in each lane)
v256i32
v512i32
For those interested in more details about Pixel Visual Core, the 6th edition of Hennessy and Patterson's "Computer Architecture: A Quantitative Approach" http://a.co/et2K1xk has a section about it (Section 7.7 pg 579-592). I'll bring my copy to the next Bay Area LLVM Socia...
2018 Jan 17
1
Does it make sense to upstream some MVT's?
...v512 instead of
> v400):
>
> v512i16
>
>
>
> 32-bit versions of the above 16-bit registers (to represent 32-bit
> accumulators for MAD instructions and also dual-issue "wide" instructions
> to the dual non-MAD ALU's in each lane)
>
> v256i32
>
> v512i32
>
>
>
>
>
> For those interested in more details about Pixel Visual Core, the 6th
> edition of Hennessy and Patterson's "Computer Architecture: A Quantitative
> Approach" http://a.co/et2K1xk has a section about it (Section 7.7 pg
> 579-592). I'll bring m...
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function