search for: v1i32

...mp;nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1, [$rbase + ( $roffset << $rshift )]", &nbsp; //&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; [(OpNode v1i16:$rs1, (add (v1i32 (bitconvert i32:$rbase)), (shl&nbsp; (v1i32 (sext v1i16:$roffset)), (v1i32 (build_vector uimm2:$rshift)) )))]&gt;; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;[(OpNode (v1i16 $rs1), (add (v1i32 (bitconvert (i32 $rbase))), (shl&nbsp; (v1i32 (sex...

...&nbsp; dag OutOperandList = (outs); &nbsp; dag InOperandList = (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift); &nbsp; string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]"; &nbsp; list<dag&gt; Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i32 (build_vector (uimm2 ?:$rshift))))))]; &nbsp; list<Register&gt; Uses = []; &nbsp; list<Register&gt; Defs = []; &nbsp; int CodeSize = 0; &nbsp; int AddedComplexity = 0; &nbsp; bit isReturn...

...nbsp; In the pattern they don’t have them.&nbsp; The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands. Could you change the pattern to &nbsp; &nbsp; [(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl&nbsp; (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))] &nbsp; -- Krzysztof Parzyszek kparzysz at quicinc.com&nbsp;&nbsp; AI tools development &nbsp; From: Celine <595602881 at qq.com&...

...leGen.cpp:253:0 #27 0x00007f163fa21830 __libc_start_main /build/glibc-LK5gWL/glibc-2.23/csu/../csu/libc-start.c:325:0 #28 0x0000000000407bd9 _start (../../../bin/llvm-tblgen+0x407bd9) =========================================================== PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2&gt;&gt;:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&a...

I am curious as to why LLVM has explicit support for 1 element vectors, for example 'v1i32'. Are there some contexts where handling a value as a 1 element vector can yield better code quality than the corresponding scalar 'i32'? Thanks, MartinO -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pi...

...riteRes<[A57UnitV]> { let Latency = 9; } def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; ``` In this code, an 128bit ASIMD FP multiply accumulate(FMLA/FMLS Q-form) requires two `A57UnitV`s, meaning that two clock cycles are needed. ^^^^^^^^^^^^^...

...v4i16 = 19, // 4 x i16 v8i16 = 20, // 8 x i16 v16i16 = 21, // 16 x i16 v2i32 = 22, // 2 x i32 So, for my platform with the 'and' I promote all i8 and i16 types, so the first type that is legal is v2i32. If I add the v1i32 then it works, however, it breaks when I added v1i16(which I need for the v2i8 case). So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around it. So it seems in this case someone has hit this issue before and added the ability to override promotion rules. > -----Original Messag...

...v4i16 = 19, // 4 x i16 v8i16 = 20, // 8 x i16 v16i16 = 21, // 16 x i16 v2i32 = 22, // 2 x i32 So, for my platform with the 'and' I promote all i8 and i16 types, so the first type that is legal is v2i32. If I add the v1i32 then it works, however, it breaks when I added v1i16(which I need for the v2i8 case). So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around it. So it seems in this case someone has hit this issue before and added the ability to override promotion rules. > -----Original Messag...

...6 > v8i16 = 20, // 8 x i16 > v16i16 = 21, // 16 x i16 > v2i32 = 22, // 2 x i32 > > So, for my platform with the 'and' I promote all i8 and i16 types, so > the first type that is legal is v2i32. > > If I add the v1i32 then it works, however, it breaks when I added > v1i16(which I need for the v2i8 case). > > So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get around > it. So it seems in this case someone has hit this issue before and > added the ability to override promotion rules. &...

...> v8i16 = 20, // 8 x i16 > v16i16 = 21, // 16 x i16 > v2i32 = 22, // 2 x i32 > > So, for my platform with the 'and' I promote all i8 and i16 types, so > the first type that is legal is v2i32. > > If I add the v1i32 then it works, however, it breaks when I added > v1i16(which I need for the v2i8 case). > > So I set AddPromotedType(ISD::AND, MVT::v4i8, MVT::v1i32) to get > around it. So it seems in this case someone has hit this issue before > and added the ability to override promotion rules...

Hi, We are now about halfway between the 3.4 and 3.5 releases, and I would like to start preparing for a 3.4.1 release. Here is my proposed release schedule: Mar 26 - April 9: Identify and backport additional bug fixes to the 3.4 branch. April 9 - April 18: Testing Phase April 18: 3.4.1 Release How you can help: - If you have any bug fixes you think should be included to 3.4.1, send me an

I don't know how your target architecture looks like, but I suspect that <4 x i8> should not be legalized to <1 x i32>. I think that what you are seeing is that <4 x i8> is first split into <2 x i8>, and later promoted to <2 x i32>. At the moment different targets can only affect type-legalization by declaring different legal types. A number of us discussed the

Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist. Micah > -----Original Message----- > From: Rotem, Nadav [mailto:nadav.rotem at intel.com] > Sent: Monday, July 30, 2012 10:51 AM > To: Villmow, Micah; Developers Mailing List > Subject: RE: Vector promotion broken