search for: v128i16

...<"ISD::MGATHER", SDTMaskedGather, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; Also, we need to make the operand $wsi a memory operand (otherwise we get the difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs to be scalar>>), like in the following complete specification: // Inspired heavily from lib/Target/X86/X86InstrInfo.td class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (...

...rn::ParseTreePattern(llvm::Init*, llvm::StringRef): Assertion `New->getNumTypes() == 1 && "FIXME: Unhandled"' failed." Can somebody help me with the code below responsible for this error? // From llvm/lib/Target/X86/X86InstrFragmentsSIMD.td def mgatherv128i16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), (masked_gather node:$src1, node:$src2, node:$src3) , [{ if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) return (mgNode->getIndex().getValueType() == MVT::v128i16 || mgNode->g...

...2:32:32-i64:64-n32:32-S128", since my back end basically extends with vector instructions the LLVM BPF back end. So, at instruction selection it lowers the <128 x i16> value to <128 x i64>, since pointers have 64 bits, which we can see from the debug info of llc: t25: v128i16 = BUILD_VECTOR Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, ... Co...

Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however...

...00, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however th...

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition.

...chmarks - things seem to work well. > > Besides these changes I added new vector types (basically all > vector types that were not already present in LLVM, from 32 lanes to > 1024, for types i8, i16, i32, i64 and f16/32/64, etc - examples of types > that I needed are v128i1, v128i16, also v1024f64). The files I changed are: > [repository]/llvm/include/llvm/CodeGen/ValueTypes.td > [repository]/lib/IR/ValueTypes.cpp > [repository]/include/llvm/IR/Intrinsics.td > [repository]/llvm/include/llvm/CodeGen/MachineValueType.h > [reposit...

...s with llc on various benchmarks - things seem to work well. Besides these changes I added new vector types (basically all vector types that were not already present in LLVM, from 32 lanes to 1024, for types i8, i16, i32, i64 and f16/32/64, etc - examples of types that I needed are v128i1, v128i16, also v1024f64). The files I changed are: [repository]/llvm/include/llvm/CodeGen/ValueTypes.td [repository]/lib/IR/ValueTypes.cpp [repository]/include/llvm/IR/Intrinsics.td [repository]/llvm/include/llvm/CodeGen/MachineValueType.h [repository]/llvm/utils/TableGen...

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it

...you might see also a bit from the error message above, is: %0 = sext <128 x i16> zeroinitializer to <128 x i64>, !dbg !17 %VectorGep = getelementptr i16, i16* inttoptr (i16 51 to i16*), <128 x i64> %0, !dbg !17 %1 = call <128 x i16> @llvm.masked.gather.v128i16(<128 x i16*> %VectorGep, i32 0, <128 x i1> <i1 true, It seems it is exactly the zeroinitializer causing the problem because if I use a different constant value than zeroinitializer it no longer gives this error. I guess LLVM gets confused by the many different types zeroinit...

Hello. I've managed to patch the various files from the back end related to lanemask - now I have 1024-bit long lanemask. But now I get the following error when giving make llc: <<error:unhandled vector type width in intrinsic!>> This error comes from this file https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp, comes from the