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Hi all, My understanding is that we keep around KILL instructions in order to keep the results of the various register liveness analysis passes valid. Consider for example the following machine basic block: BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %A1_64 %V0_64<def> = AND64 %A0_64<kill>, %A1_64<kill> %V0<def> = KILL %V0, %V0_64<imp-use,kill> PseudoReturn64 %RA_64 In this case we would like to move the AND64 instruction after the KILL instruction (generated from an identity COPY). What is the right thing to d...

Thanks for your reply Quentin. I do understand that the registers are allocated much later in the pipeline. I am assuming that the physical registers are allocated before MipsAsmPrinter class. I am doing something like if (MI->getOpcode() == Mips::OPCODE) { unsigned n = MI->getNumOperands(); for(unsigned i=0 ; i < n ; i++) { const MachineOperand &MO =

On 11 January 2017 at 10:24, Jim Grosbach via llvm-dev <llvm-dev at lists.llvm.org> wrote: > ARM64 is like this. I suggest having a look at that backend (lib/Target/AArch64) and how it deals with implicit zeroing of the upper bits of the X registers. ARM64 has a separate name for the registers as 32-bit values though (W0-W30 rather than X0-X30). I could easily see DAG ISel throwing a fit

> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) >

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32* @b, align 4, !tbaa !1 %1