Displaying 5 results from an estimated 5 matches for "d0_64".
2012 Jan 31
4
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...: FPR< 0, "F0">, DwarfRegNum<[32]>;
/// Mips Double point precision FPU Registers (aliased
/// with the single precision to hold 64 bit values)
def D0 : AFPR< 0, "F0", [F0, F1]>;
/// Mips Double point precision FPU Registers in MFP64 mode.
def D0_64 : AFPR64<0, "F0", [F0]>;
Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
The examples here are from lib/Target/Mips/MipsRegisterInfo.td.
Do I just need to use/write another register parser? Or is there a clever way of definin...
2015 Feb 28
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Thanks for your reply Quentin. I do understand that the registers are
allocated much later in the pipeline.
I am assuming that the physical registers are allocated before
MipsAsmPrinter class.
I am doing something like
if (MI->getOpcode() == Mips::OPCODE) {
unsigned n = MI->getNumOperands();
for(unsigned i=0 ; i < n ; i++) {
const MachineOperand &MO =
2012 Feb 02
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...DwarfRegNum<[32]>;
>
> /// Mips Double point precision FPU Registers (aliased
> /// with the single precision to hold 64 bit values)
> def D0 : AFPR< 0, "F0", [F0, F1]>;
>
> /// Mips Double point precision FPU Registers in MFP64 mode.
> def D0_64 : AFPR64<0, "F0", [F0]>;
>
> Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
>
> The examples here are from lib/Target/Mips/MipsRegisterInfo.td.
>
> Do I just need to use/write another register parser? Or is...
2012 Feb 03
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...DwarfRegNum<[32]>;
>
> /// Mips Double point precision FPU Registers (aliased
> /// with the single precision to hold 64 bit values)
> def D0 : AFPR< 0, "F0", [F0, F1]>;
>
> /// Mips Double point precision FPU Registers in MFP64 mode.
> def D0_64 : AFPR64<0, "F0", [F0]>;
>
> Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
>
> The examples here are from lib/Target/Mips/MipsRegisterInfo.td.
>
> Do I just need to use/write another register parser? Or is...
2015 Feb 27
0
[LLVMdev] LLVM register number for MIPS DAGToDAG
> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote:
>
> Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class?
>
> More Specifically:
> SDValue Reg3 = Node->getOperand(3);
> if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3))
>