search for: uvd

http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=4d60422 also broken with this commit

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Boyuan Zhang (1): tests/amdgpu: add uvd encode unit tests Chih-Wei Huang (2): android: add rules to build amdgpu.ids android: amdgpu: fix build break Daniel Stone (1): configure.ac: Bump version to 2.4.83 Emil Velikov (1): xf86drm: continue with next device if drmProcessUsbDevice fails Eric Engestrom (4):...

...intel: Change a KBL pci id to GT2 from GT1.5 Christian König (1): amdgpu: make userptr unit test more interesting Dave Airlie (1): headers: sync syncobj ioctl defines. Eric Engestrom (1): freedreno/kgsl: fix pointer-to-int cast James Zhu (2): tests/amdgpu: add new uvd enc support check tests/amdgpu: fix uvd enc data corruption issue Jan Vesely (1): amdgpu: Do not write beyond allocated memory when parsing ids Marek Olšák (7): amdgpu: print error messages when amdgpu_device_initialize is failing include: sync drm.h and amdgpu_drm.h with...

...in question we actually do the reset and everything is fine. In your example we would do the reset when the next X server starts, before that point nobody would care because nobody uses the hardware. An additional problem here is that resets are something perfect normal for radeon. For example UVD can "crash" when you feed it with invalid bitstream data, (ok actually it send an interrupt and stops any processing for the driver to investigate). To continue processing you need to go through a rather complicated reset procedure. Christian. > -Daniel

On Wed, Jul 23, 2014 at 9:06 AM, Maarten Lankhorst <maarten.lankhorst at canonical.com> wrote: >> Can we somehow avoid the need to call fence_signal() at all? The interrupts at least on radeon are way to unreliable for such a thing. Can enable_signalling fail? What's the reason for fence_signaled() in the first place? > It doesn't need to be completely reliable, or finish

...re sending them to the CPU, e.g. you can get one interrupt for multiple fences finished. If it's just the interrupt for the last fence submitted that gets lost you are completely screwed up because you won't get another interrupt. > > I had that problem multiple times while working on UVD support, resulting in the driver thinking that it can't submit more jobs because non of the interrupts for the already submitted fence cam through. Yeah but all the fences that have .enable_signaling will get signaled from a single interrupt, or when any waiter calls radeon_fence_process. >...

...CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1"; > + case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2"; > + case R600_RING_TYPE_DMA_INDEX: return "radeon.dma"; > + case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1"; > + case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd"; Radeon supports vce rings on newer ascis. Probably want to add the case for those here too. Alex > + default: WARN_ON_ONCE(1); return "radeon.unk"; > + } > +} > + > +static const struct fence_ops radeon_fence_ops = { > + .get_dri...

...ect good b4b50b074beae9b679e5acdbb4b49193e539576d # good: [60c08aa90bce4c8766a747c8517f7ff6987937f0] gallium/radeon: disable CMASK on handle export if sharing doesn't allow it (v2) git bisect good 60c08aa90bce4c8766a747c8517f7ff6987937f0 # good: [8be9efcce70f671afcaf3cfc76c624b3467b7834] radeon/uvd: handle HEVC main 10 decode git bisect good 8be9efcce70f671afcaf3cfc76c624b3467b7834 # bad: [c1e4a6bfbf015801c6a8b0ae694482421a22c2d9] nv50,nvc0: handle SQRT lowering inside the driver git bisect bad c1e4a6bfbf015801c6a8b0ae694482421a22c2d9 # good: [a651bc027d5ed4150bb5240fc9f46a6ca569f665] nvc0: f...

...ix memory leak on ringbuffer free Rob Herring (1): Android: strip out header files from sources list Rodrigo Vivi (2): intel: Add more Kabylake PCI IDs. intel: Removing PCI IDs that are no longer listed as Kabylake. Sonny Jiang (1): tests/amdgpu: adapt to new polaris10/11 uvd fw git tag: libdrm-2.4.69 http://dri.freedesktop.org/libdrm/libdrm-2.4.69.tar.bz2 MD5: 2cee933bdef3e10d552d97b3a8fb640f libdrm-2.4.69.tar.bz2 SHA1: 024ad2d208180129194b47492317adedf76fda41 libdrm-2.4.69.tar.bz2 SHA256: 09510cbc75adba7e84fd3ec86586fd352a787fd534a63377de9e19ff85280b33 libdrm-2....

...autogen.sh: run git commands in the (potentially) git dir Huang Rui (2): amdgpu: don't read registers not present on Vega10 tests/amdgpu: fix the count number for vega10 Junwei Zhang (1): tests/amdgpu: add Polaris12 support for cs test Leo Liu (3): tests/amdgpu: add uvd unit test support for vega10 tests/amdgpu: add vce unit test support for vega10 amdgpu_drm: add AMDGPU_HW_IP_UVD_ENC Marek Olšák (3): amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2 amdgpu: update amdgpu_drm.h for Vega10 configure.ac: bump version for release Rob Clar...

...d before sending them to the CPU, e.g. you can get one interrupt for multiple fences finished. If it's just the interrupt for the last fence submitted that gets lost you are completely screwed up because you won't get another interrupt. I had that problem multiple times while working on UVD support, resulting in the driver thinking that it can't submit more jobs because non of the interrupts for the already submitted fence cam through. Apart from that interrupts on Macs usually don't work at all, so we really need a solution where calling fence_signaled() is completely op...

...actually do the reset and everything is fine. > > In your example we would do the reset when the next X server starts, before that point nobody would care because nobody uses the hardware. > > An additional problem here is that resets are something perfect normal for radeon. For example UVD can "crash" when you feed it with invalid bitstream data, (ok actually it send an interrupt and stops any processing for the driver to investigate). To continue processing you need to go through a rather complicated reset procedure. In this case if the sync was to i915 the i915 lockup pro...

...kedev live in <sys/sysmacros.h> Eric Anholt (1): headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI. Eric Engestrom (2): headers: sync drm_fourcc.h with airlied/drm-next headers: sync drm_sarea.h with airlied/drm-next Leo Liu (5): tests/amdgpu: rename uvd messages to decode messages tests/amdgpu: separate decode messages tests/amdgpu: move decode sum to common tests/amdgpu: add vcn tests support and sets tests/amdgpu: implement vcn dec unit tests Lucas Stach (1): configure.ac: bump version for release Michel Dänzer (...

...E_CP1_INDEX: return "radeon.cp1"; >> + case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2"; >> + case R600_RING_TYPE_DMA_INDEX: return "radeon.dma"; >> + case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1"; >> + case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd"; > Radeon supports vce rings on newer ascis. Probably want to add the case for those here too. > > Alex > Indeed, how about this? ----------8<------- Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- drivers/gpu/drm...

...tate const data as such for good measure libkms: use static const for good measure radeon: cleanup bo/cs func tables freedreno: annotate the device/bo/pipe/ringbuffer funcs as const data tests/amdgpu: reference the correct variable for memcpy tests/amdgpu: annotate the uvd message templates as const data tests/amdgpu: annotate (most of) the vce templates as const data tests/amdgpu: ensure tests work by using c99 initializers nouveau: use designated initializers intel: ignore missing-field-initializers warnings configure: remove -Wno-miss...

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...om/bgmilne.asc 1024D/60D204A7 2919 E232 5610 A038 87B1 72D6 AC92 BA50 60D2 04A7 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.2 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQE/fA3YrJK6UGDSBKcRAlaEAKC+S3rCZtv+/kYnvGOTDKQXQIPu/ACgqLw6 Oj8mtGPI1jkl4+Irde7isqA= =/uvD -----END PGP SIGNATURE----- ***************************************************************** Please click on http://www.cae.co.za/disclaimer.htm to read our e-mail disclaimer or send an e-mail to info@cae.co.za for a copy. *****************************************************************

> Regardless of the fence implementation, why would it be a good idea to do a full lockup recovery when some other driver is > calling your wait function? That doesn't seem to be a nice thing to do, so I think a timeout is the best error you could return here, > other drivers have to deal with that anyway. The problem is that we need to guarantee that the lockup will be resolved

...ry amdgpu: add ce_ram_size for interface query amdgpu: add ib_start_alignment and ib_size_alignment for interface query amdgpu: add base_preferred parameter to amdgpu_vamgr_find_va amdgpu : move management of user fence from libdrm to UMD test/amdgpu : fix a bug in VCE/UVD test introduced by previous change Kristian Høgsberg Kristensen (1): intel: Drop aub dumping functionality Leo Liu (2): tests/amdgpu: implement VCE unit tests amdgpu: add VCE harvesting instance query Marek Olšák (15): amdgpu: implement amdgpu_cs_query_reset_state a...

...on.gfx"; + case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1"; + case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2"; + case R600_RING_TYPE_DMA_INDEX: return "radeon.dma"; + case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1"; + case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd"; + default: WARN_ON_ONCE(1); return "radeon.unk"; + } +} + +static const struct fence_ops radeon_fence_ops = { + .get_driver_name = radeon_fence_get_driver_name, + .get_timeline_name = radeon_fence_get_timeline_name, + .enable_signaling = radeon_fence_...