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...nstructions which operates on 64bit operands, take pairs of 32bit registers. However in some of these instructions registers are encoded as a pair number and in some as two single register numbers for each pair. Similar problem with immediates which not fit in 10bits - they are encoded as separate upper22 bits and lower10 bits (64 bits long version of instruction instead of 32 bits). Thanks a lot for explanation/suggestions Artur -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100222/cda06138/attachment.html&...

...es on 64bit operands, > take pairs of 32bit registers. However in some of these instructions > registers are encoded as a pair number and in some as two single register > numbers for each pair. > Similar problem with immediates which not fit in 10bits - they are encoded > as separate upper22 bits and lower10 bits (64 bits long version of > instruction instead of 32 bits). So, what's the problem here? All such weirdness should be handled inside code emitter.... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hello, Artur > I have defined registers, aliases and subregister set. > The problem is that register allocator is using 32bit registers that are > already used in a pair, for example: > lw $r0, 16[$r12]   // load word to r0 > ld $p0, 36[$r12]   // load doubleword to p0 > shl $p0, $p0, $r0    // shift left p0 by r0  and store result in p0 > where p0 is a pair r0:r1 > Could

Hi All, My target has 32bit registers, but it has some 64bit instructions which are using pairs of these 32bit registers. I have defined registers, aliases and subregister set. The problem is that register allocator is using 32bit registers that are already used in a pair, for example: lw $r0, 16[$r12] // load word to r0 ld $p0, 36[$r12] // load doubleword to p0 shl $p0, $p0, $r0 // shift