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Commit 'drm/nv50-nvc0/vm: support unsnooped system memory' caused a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=45746 Reported-by: Johannes Obermayr <johannesobermayr at gmx.de> Tested-by: Johannes Obermayr <johannesobermayr at...

...to much of a problem. We do support USWC on radeon, although I think we had separate flags for cached and WC. That said we had a lot of problems with WC on 32 bit (see radeon_bo_create()). The other problem is that, at least on the really old radeons, the PCI gart didn't support snooped and unsnooped. It was always snooped. It wasn't until pcie that the gart hw got support for both. For AGP, the expectation was that AGP provided the uncached memory. > > > Summing it up I'm still leaning towards disabling AGP completely by > default for radeon and deprecate it in TTM as...

https://bugs.freedesktop.org/show_bug.cgi?id=45746 Bug #: 45746 Summary: ION (NVAC) does not work with latest git kernel module Classification: Unclassified Product: xorg Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau

...ship transition from user to GPU > is always clearly performed by syscalls), and use coherent mappings for > buffers used by the kernel which are accessed more randomly. This has solved > all our coherency issues and resulted in the best performance so far. I wonder if we might want to use unsnooped cached mappings of pages on non-ARM platforms also, to avoid the overhead of the cache snooping? > > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel

...w to determine what happens to the packet afterwards. Is there a Dtrace script that follows a packet queued bia send(2) or sendto(2) through the kernel/stack and can indicate whether some low-level function returns a failure, or possibly hands it to a different interface (we snooped all except the unsnoopable lo though w/o luck).. I looked at the Dtrace Networking Guide but without more knowledge of internals it was no help. PS: The Solaris-10 machine I work on is old, so it has no ip nor udp provider, but if it takes that I''d also like to know. any hints on where to start would be welco...

...> +++ b/include/uapi/drm/nouveau_drm.h > @@ -36,6 +36,7 @@ > #define NOUVEAU_GEM_TILE_32BPP 0x00000002 > #define NOUVEAU_GEM_TILE_ZETA 0x00000004 > #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 > +#define NOUVEAU_GEM_TILE_WCUS 0x00000010 /* write-combined, unsnooped */ > > struct drm_nouveau_gem_info { > uint32_t handle; > -- > 1.8.3.1 >

...nclude/uapi/drm/nouveau_drm.h +++ b/include/uapi/drm/nouveau_drm.h @@ -36,6 +36,7 @@ #define NOUVEAU_GEM_TILE_32BPP 0x00000002 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 +#define NOUVEAU_GEM_TILE_WCUS 0x00000010 /* write-combined, unsnooped */ struct drm_nouveau_gem_info { uint32_t handle; -- 1.8.3.1

...gt; We do support USWC on radeon, although I think we had separate flags > for cached and WC. That said we had a lot of problems with WC on 32 > bit (see radeon_bo_create()). The other problem is that, at least on > the really old radeons, the PCI gart didn't support snooped and > unsnooped. It was always snooped. It wasn't until pcie that the gart > hw got support for both. For AGP, the expectation was that AGP > provided the uncached memory. Oh, indeed. I didn't remembered that. Interesting is that in this case I have no idea where the performance difference is...

...rom user to GPU >> is always clearly performed by syscalls), and use coherent mappings for >> buffers used by the kernel which are accessed more randomly. This has solved >> all our coherency issues and resulted in the best performance so far. > I wonder if we might want to use unsnooped cached mappings of pages on > non-ARM platforms also, to avoid the overhead of the cache snooping? You might want to indeed, now that coherency is guaranteed by the sync functions originally introduced by Lucas. The only issue I could see is that they always invalidate the full buffer where...

This is the first set of patches to make Nouveau work on Tegra. Those are only the obvious correctness fixes, a lot of optimization work remains to be done, but at least it's enough to get accel working and let the machine survive a piglit run. A new BO flag is introduced to allow userspace to hint the kernel about possible optimizations. Lucas Stach (6): drm/ttm: recognize ARM arch in

...ove another sna_pixmap->cpu assertion that was not true sna/gen2: Tidy DBG code for disabling composite operations sna: Refactor the fallback CopyArea to use the common region computation configure: Make rebuilding of the gen4 assembly files explicit sna: Do not create an unsnooped CPU mapping for readbacks sna/gen2: Add a couple of assertions to track down a batch overflow sna/gen2: Compile fix sna/gen2: And the other compile failure Use path for intel-gen4asm derived from pkg-config sna/gen2: Count the number of dwords required for the invari...

On Tue, Jul 08, 2014 at 05:25:57PM +0900, Alexandre Courbot wrote: > page_to_phys() is not the correct way to obtain the DMA address of a > buffer on a non-PCI system. Use the DMA API functions for this, which > are portable and will allow us to use other DMA API functions for > buffer synchronization. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > ---

Unfortunately AGP is still to widely used as we could just drop support for using its GART. Not using the AGP GART also doesn't mean a loss in functionality since drivers will just fallback to the driver specific PCI GART. For now just deprecate the code and don't enable the AGP GART in TTM even when general AGP support is available. Please comment, Christian.