search for: unk21

Displaying 9 results from an estimated 9 matches for "unk21".

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2013 Jul 18
1
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
...ivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -73,7 +73,8 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq, struct nouveau_fb *pfb = nouveau_fb(device); struct nouveau_drm *drm = nouveau_drm(dev); struct bit_entry P; - uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3; + uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tUnk_3_2; + int tUNK_base; if (bit_table(dev, 'P', &P)) return -EINVAL; @@ -91,6 +92,11 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq, break; } + tUnk_3_2 = (boot->reg[3] & 0x00ff0000) >> 16; +...
2013 Jul 18
0
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
....c > +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c > @@ -73,7 +73,8 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq, > struct nouveau_fb *pfb = nouveau_fb(device); > struct nouveau_drm *drm = nouveau_drm(dev); > struct bit_entry P; > - uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3; > + uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tUnk_3_2; > + int tUNK_base; > > if (bit_table(dev, 'P', &P)) > return -EINVAL; > @@ -91,6 +92,11 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq, > break; > } > > + tUnk...
2013 Dec 08
2
[PATCH 1/3] nv50: enable h264 and mpeg4 for nv98+ (vp3, vp4.0)
Create the ref_bo without any storage type flags set for now. The issue probably arises from our use of the additional buffer space at the end of the ref_bo. It should probably be split up in the future. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Tested-by: Martin Peres <martin.peres at labri.fr> Cc: "10.0" <mesa-stable at lists.freedesktop.org> ---
2012 Jun 25
1
[PATCH 1/2] drm/nouveau/pm: Prepare for more GDDR5 MR values
v2: style fixes Signed-off-by: Roy Spliet <r.spliet at student.tudelft.nl> --- drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- drivers/gpu/drm/nouveau/nouveau_mem.c | 25 +++++++++++++++++++------ 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index b8fa77d..fe242a3 100644 ---
2016 Mar 02
0
Debugging second dvi output on quadro fx380 not working
...CLOCK.SOR[0x1] <= 0x3074080 [0] 443.964307 MMIO32 R 0x61630c 0x01220000 PDISPLAY+0x630c => 0x1220000 [0] 443.964322 MMIO32 W 0x61630c 0x01220000 PDISPLAY+0x630c <= 0x1220000 [0] 443.964347 MMIO32 R 0x00e1b8 0x7fffffff PNVIO.IBUF_ENABLE_0 => { GPIO_0_15 = 0xffff | I2C_0_3 = 0xf | I2C_5 | UNK21 = 0x1f | UNK26 | UNK27 = 0xf } [0] 443.964366 MMIO32 W 0x00e1b8 0x7e7fffff PNVIO.IBUF_ENABLE_0 <= { GPIO_0_15 = 0xffff | I2C_0_3 = 0xf | I2C_5 | UNK21 = 0x13 | UNK26 | UNK27 = 0xf } [0] 443.964386 MMIO32 R 0x00e600 0xa0400000 PNVIO+0x600 => 0xa0400000 [0] 443.964406 MMIO32 R 0x00e610 0x7c0a00...
2013 Dec 07
1
H.264 engine differences between fermi and tesla cards
...rm > unsigned notseenyet : 1; // 00 15 pad? -> not_existing > unsigned unk16 : 1; // 00 16 -> is_field_pair > unsigned unk17 : 4; // 00 17..20 -> top_field_marking (top_is_reference ? 1+is_long_term : 0) > unsigned unk21 : 4; // 00 21..24 -> bottom_field_marking > unsigned pad : 7; // 00 d25..31 > > uint32_t field_order_cnt[2]; // 04,08 > uint32_t frame_idx; // 0c > } refs[0x10]; > > uint8_t m4x4[6][16]; // 140 > uint...
2013 Nov 30
2
H.264 engine differences between fermi and tesla cards
On Thu, Nov 21, 2013 at 5:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Nov 21, 2013 at 5:07 PM, Benjamin Morris <bmorris at nvidia.com> wrote: >> On 11/19/2013 08:16 PM, Ilia Mirkin wrote: >>> Hello, >>> >>> I hope this is an appropriate style of request for this forum. I added >>> code to support video decoding on the tesla
2013 Dec 07
0
H.264 engine differences between fermi and tesla cards
...bottom_is_reference unsigned unk14 : 1; // 00 14 skipped? -> is_long_term unsigned notseenyet : 1; // 00 15 pad? -> not_existing unsigned unk16 : 1; // 00 16 -> is_field_pair unsigned unk17 : 4; // 00 17..20 -> top_field_marking (top_is_reference ? 1+is_long_term : 0) unsigned unk21 : 4; // 00 21..24 -> bottom_field_marking unsigned pad : 7; // 00 d25..31 uint32_t field_order_cnt[2]; // 04,08 uint32_t frame_idx; // 0c } refs[0x10]; uint8_t m4x4[6][16]; // 140 uint8_t m8x8[2][64]; // 1a0 // most of the remaining is MVC or SVC setup info, filled zero if not MVC or...
2013 Aug 11
10
[PATCH 00/10] Add support for MPEG2 and VC-1 on VP3/VP4 for NV98-NVAF
As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which