Displaying 5 results from an estimated 5 matches for "unguided".
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2012 Jun 13
2
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
...the TypeLegalizeActions is not open to the
particular target implementations, I just did a quick and dirty hack
to tell the TypeLegalizer to expand operations on MVT::i64 values.
Though, this triggers an assertion in
"SelectionDAGLegalize::LegalizeOp".
Before I am going to do more "unguided hacking and guessing", I want
to task if there is an "official way" to support the setup described
above, i.e. having instructions working an 64bit registers (composed
of pairs of 32bit registers) without true support for MVT::i64 values.
Ciao, Fabian
2012 Jun 13
0
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
...t open to the
> particular target implementations, I just did a quick and dirty hack
> to tell the TypeLegalizer to expand operations on MVT::i64 values.
> Though, this triggers an assertion in
> "SelectionDAGLegalize::LegalizeOp".
>
> Before I am going to do more "unguided hacking and guessing", I want
> to task if there is an "official way" to support the setup described
> above, i.e. having instructions working an 64bit registers (composed
> of pairs of 32bit registers) without true support for MVT::i64 values.
>
> Ciao, Fabian
> _...
2012 Jul 12
0
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
On Thu, Jul 12, 2012 at 01:22:39PM +0200, Fabian Scheler wrote:
> Hi Micah,
>
> > We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
> >
> > What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
>
> thanks for your hint. Unfortunately, I didn't find any
2012 Jul 18
1
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
...and it
> doesn't look like there is an Expand operation implemented for
> ISD::Constant. I think you'll either need implement Expand for
> ISD::Constant or Custom lower it in your backend.
thank you for that information. This exactly is what I feared. Well I
did some more mostly unguided hacking and these are the opportunities
I found/was pointed to:
1. Implement custom lowering in the backend
(cf. eg. SDNode *PPCDAGToDAGISel::Select(SDNode *N))
It is not a big issue to split the constant in the 32 higher and lower
bits and to load these fragments separately. However, I don'...
2012 Jul 12
2
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
Hi Micah,
> We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer