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I have one of those new little NUC's and installed Centos 7.1 on it. lspci shows 00:00.0 Host bridge: Intel Corporation Haswell-ULT DRAM Controller (rev 09) 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) 00:03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09) 00:14.0 USB controller: Intel Corporation 8 Series USB xHCI HC (rev 04) 00:16.0 Communic...

For void test0(unsigned short a, unsigned short * in, unsigned short * out) { for (unsigned short w = 1; w < a - 1; w++) //this will never overflow out[w] = in[w+7] * 2; } I think it will be sufficient to add a couple of new cases to ScalarEvolution::HowManyLessThans -- zext(A) ult zext(B) == A ult B sext(A) slt sext(B) == A slt B Currently it bails out if it sees a non-add recurrence on the LHS of the ult/slt. You could also teach ScalarEvolution::isImpliedCondOperands the following: zext(A) ult zext(B) <=> A ult B sext(A) slt sext(B) <=> A slt B to get...

Hi, I'm from Argentina, this model isn't in the hardware compatibility list: Lyonn ULT-2000 MKR http://www.solytec.com.ar/p03_ups_lyonn_ult1000.php http://www.solytec.com.ar/p03_ups_lyonn_ultrack.php How can I do to control via SNMP? I have an AgentMini hardware. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.alioth.debian....

Hi, I am investigating a performance degradation between llvm-3.1 and llvm-3.2 (Note: current top-of-tree shows a similar degradation) One issue I see is the following: - 'loop invariant code motion' seems to be depending on the result of the 'reassociate expression' pass: In the samples below I observer the following behavior: Both start with the same expression: %add = add i32 %total.0, %next.0 %add1 = add i32 %add, 1 -LLVM-3.1 converts this into: --after Reassociate expressions: %add = add i32 %next.0, 1 %ad...

As far as I can understand of the code, the Reassociate tries to achieve this result by its "ranking" mechanism. If it dose not, it is not hard to achieve this result, just restructure the expression in a way such that the earlier definition of the sub-expression is permute earlier in the resulting expr. e.g. outer-loop1 x= outer-loop2 y...

...Reassociate; as usual, the documentation resolutely avoids giving any credit for the ideas. Why is that? Preston > On Apr 23, 2013, at 10:37 AM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > > > As far as I can understand of the code, the Reassociate tries to achieve this result by its "ranking" mechanism. > > > > If it dose not, it is not hard to achieve this result, just restructure the expression in a way such that > > the earlier definition of the sub-expression is permute earlier in the resulting expr. > > > > e.g. > > o...

...), an ARM target is stuck at 19 IR instructions: declare void @use4(i8, i8, i8, i8) define void @min_of_3_vals(i8 %x, i8 %y, i8 %z) { %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 %nz = xor i8 %z, -1 %zx = zext i8 %nx to i32 %zy = zext i8 %ny to i32 %zz = zext i8 %nz to i32 %cmpxz = icmp ult i32 %zx, %zz %minxz = select i1 %cmpxz, i32 %zx, i32 %zz %cmpyz = icmp ult i32 %zy, %zz %minyz = select i1 %cmpyz, i32 %zy, i32 %zz %cmpyx = icmp ult i8 %y, %x %minxyz = select i1 %cmpyx, i32 %minxz, i32 %minyz %tr_minxyz = trunc i32 %minxyz to i8 %new_zx = sub nsw i32 %zx, %minxyz...

...n resolutely avoids giving any credit for the ideas. > Why is that? > > Preston > > > > On Apr 23, 2013, at 10:37 AM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > > > > > As far as I can understand of the code, the Reassociate tries to achieve this result by its "ranking" mechanism. > > > > > > If it dose not, it is not hard to achieve this result, just restructure the expression in a way such that > > > the earlier definition of the sub-expression is permute earlier in the resulting expr. > > > > &gt...

...t have a complete HCL report.) > > > On May 26, 2016, at 10:44 AM, Marcos Martinez <marcosdmm at gmail.com <mailto:marcosdmm at gmail.com>> wrote: > > > > Hi, I'm from Argentina, this model isn't in the hardware compatibility list: > > > > Lyonn ULT-2000 MKR > > > > http://www.solytec.com.ar/p03_ups_lyonn_ult1000.php <http://www.solytec.com.ar/p03_ups_lyonn_ult1000.php> > > http://www.solytec.com.ar/p03_ups_lyonn_ultrack.php <http://www.solytec.com.ar/p03_ups_lyonn_ultrack.php> > > > > > > How ca...

Hi, anyone has configured NUT with an UPS Lyonn 2000-ULT KRM??? It isn't in the hardware compatibility list. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.alioth.debian.org/pipermail/nut-upsuser/attachments/20160523/e29cbeb0/attachment.html>

...mobj = bitcast i8* %mem to i64* %ptr = getelementptr inbounds i64* %memobj, i64 %index %4 = load i64* %ptr, align 8 Currently, the IR for bounds checking this load looks like this: %size = mul i64 8, %elements %offset = mul i64 %index, 8 %objsize = sub i64 %size, %offset %cmp2 = icmp ult i64 %size, %offset %cmp3 = icmp ult i64 %objsize, 8 %cmp1 = icmp slt i64 %offset, 0 %9 = or i1 %cmp2, %cmp3 %11 = or i1 %cmp1, %9 br i1 %11, label %trap, label %12 ┆ ┆ │ │ ╴╴╴╴╴╴╴╴╴╴╴╴╴╴╴╴╴╴┢━━━━━━━┪╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶╶ ↑...

...%3 = add i32 %2, %n %4 = icmp ult i32 %2, %3 br i1 %4, label %.lr.ph3, label %._crit_edge...

...n Phabricator. If we can squash any of the regressions before that goes in, that would be even better. On Mon, Jan 22, 2018 at 3:10 AM, David Green <David.Green at arm.com> wrote: > Hello > > Thanks for looking into this. > > I can't be very confident what the knock on result of a change like that > would be, > especially on architectures that are not Arm. What I can do though, is run > some > benchmarks and look at that results. > > Using this patch: > > --- a/lib/Transforms/InstCombine/InstructionCombining.cpp > +++ b/lib/Transforms/InstComb...

Hello Thanks for looking into this. I can't be very confident what the knock on result of a change like that would be, especially on architectures that are not Arm. What I can do though, is run some benchmarks and look at that results. Using this patch: --- a/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -150,6 +150...

While looking at what llvm writes for this testcase, I noticed that there is one redundant operation in resulting assembly. The second 'cmp' operation there is essentially identical to the first one, with reversed order of arguments. Therefore, it is not needed. This testcase is a simple integer comparison routine, similar to what qsort would take to sort an integer array. I think llvm should b...

...that would be an implicit pass dependency, which is against the rules. Ok, consider this LLVM IR code fragment: br i1 %overflow_check, label %no_overflow, label %end no_overflow: %t0 = add nsw i32 %a, %b %t1 = sext i32 %t0 to i64 %t2 = ashr i64 %t1, 31 %t3 = add i64 %t2, 1 %t5 = icmp ult %t3, 2 %t6 = udiv i1 1, %t5 Assume label %no_overflow has no other predecessors. And assume adding %a and %b can sometimes produce overflow, but only when %overflow_check is false. This code has no undefined behavior. It's a bit subtle, but in particular, note that it's not possible for...

...pm > vs > xorg-x11-drv-intel-2.99.916-5.el7.x86_64 > > Are you searching for the 2.99.917 one ? > Thanks to both. Fabian, I am searching a driver that simply works :)) My laptop has a Hasweel motherboard with an Intel Graphics HD 4400: 00:00.0 Host bridge: Intel Corporation Haswell-ULT DRAM Controller (rev 09) 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) 00:03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09) 00:14.0 USB controller: Intel Corporation 8 Series USB xHCI HC (rev 04) 00:16.0 Communic...

...for the ideas. > > Why is that? > > > > Preston > > > > > > > On Apr 23, 2013, at 10:37 AM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > > > > > > > As far as I can understand of the code, the Reassociate tries to achieve this result by its "ranking" mechanism. > > > > > > > > If it dose not, it is not hard to achieve this result, just restructure the expression in a way such that > > > > the earlier definition of the sub-expression is permute earlier in the resulting expr. > &gt...

...r = getelementptr inbounds i64* %memobj, i64 %index > %4 = load i64* %ptr, align 8 > > Currently, the IR for bounds checking this load looks like this: > > %size = mul i64 8, %elements > %offset = mul i64 %index, 8 > %objsize = sub i64 %size, %offset > > %cmp2 = icmp ult i64 %size, %offset > %cmp3 = icmp ult i64 %objsize, 8 > %cmp1 = icmp slt i64 %offset, 0 > > %9 = or i1 %cmp2, %cmp3 > %11 = or i1 %cmp1, %9 > br i1 %11, label %trap, label %12 > > ┆ ┆ > │ │ > ╴╴╴╴╴╴╴╴╴╴╴╴╴╴╴...

...However, I don’t see this behavior when trying to compile this variant of the mentioned “typical naive fib implementation”: unsigned int fib(unsigned int n) { return n < 2 ? n : fib(n-1) + fib(n-2); } The IR with clang -O3 (version 3.4) is this: define i32 @_Z9fibj(i32 %n) #0 { %1 = icmp ult i32 %n, 2 br i1 %1, label %8, label %2 ; <label>:2 ; preds = %0 %3 = add i32 %n, -1 %4 = tail call i32 @_Z9fibj(i32 %3) %5 = add i32 %n, -2 %6 = tail call i32 @_Z9fibj(i32 %5) %7 = add i32 %6, %4 ret i32 %7 ; <label>:8...