search for: u16imm

...16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC backend, which has the exact same issue > for integer constants. Actually, for SPU, not quite the same: def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val), "ilhu $rT, $val", LoadNOP, [(set GPRC:$rT, immZExt16:$val)]>; def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val), "iohl $rT, $val", LoadNOP, [(set GPRC:$rT, immZExt16:$val)]&g...

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

...m in >>> X86InstrSSE.td as an example. >> >> >> Another good example is the PPC backend, which has the exact same >> issue >> for integer constants. > > Actually, for SPU, not quite the same: > > def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val), > "ilhu $rT, $val", LoadNOP, > [(set GPRC:$rT, immZExt16:$val)]>; > > def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val), > "iohl $rT, $val", LoadNOP, > [(set...

...s11_3ImmPred:$offset)))]>; >> >> let mayLoad = 1, neverHasSideEffects = 1 in >> -def LDrid_GP : LDInst<(outs DoubleRegs:$dst), >> +def LDrid_GP : LDInst2<(outs DoubleRegs:$dst), >> (ins globaladdress:$global, u16Imm:$offset), >> "$dst=memd(#$global+$offset)", >> []>; >> >> let mayLoad = 1, neverHasSideEffects = 1 in >> -def LDd_GP : LDInst<(outs DoubleRegs:$dst), >> +def LDd_GP : LDInst2<(outs DoubleRegs:$dst), >>...