search for: tsc_scale

...page *tsc_pg = > + (const struct ms_hyperv_tsc_page *)&hvclock_page; > + u64 sequence, scale, offset, current_tick, cur_tsc; > + > + while (1) { > + sequence = READ_ONCE(tsc_pg->tsc_sequence); > + if (!sequence) > + break; > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + rdtscll(cur_tsc); > + > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset; > + > + if (READ_ONCE(tsc_pg->tsc_sequence) == sequence) > + return current_tick; That sequence stuff lacks still a sensible exp...

...page *tsc_pg = > + (const struct ms_hyperv_tsc_page *)&hvclock_page; > + u64 sequence, scale, offset, current_tick, cur_tsc; > + > + while (1) { > + sequence = READ_ONCE(tsc_pg->tsc_sequence); > + if (!sequence) > + break; > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + rdtscll(cur_tsc); > + > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset; > + > + if (READ_ONCE(tsc_pg->tsc_sequence) == sequence) > + return current_tick; That sequence stuff lacks still a sensible exp...

...this is only case here. Also since this failure only occurs if host clock is not available, probably should be unlikely. > + /* > + * Make sure we read sequence before we read other values from > + * TSC page. > + */ > + smp_rmb(); > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + cur_tsc = rdtsc_ordered(); Since you already have smp_ barriers and rdtsc_ordered is a barrier, the compiler barriers (READ_ONCE()) shouldn't be necessary. > + > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset;...

...this is only case here. Also since this failure only occurs if host clock is not available, probably should be unlikely. > + /* > + * Make sure we read sequence before we read other values from > + * TSC page. > + */ > + smp_rmb(); > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + cur_tsc = rdtsc_ordered(); Since you already have smp_ barriers and rdtsc_ordered is a barrier, the compiler barriers (READ_ONCE()) shouldn't be necessary. > + > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset;...

Hi Ian/Stefano: I changed over to the PV clock for hybrid liked we talked at the hackathon. I still have the hang in update_wall_time() after dom0 switches to xen as clocksource. The source of hang seems to be in xen stime_local_stamp in cpu_time that suddenly jumps to a large 64bit value. I''ve been chasing to figure where that happens, and why for the hybrid and not PV. It appears the

...= -ENOSYS; break; diff -r 256160ff19b7 xen/arch/x86/time.c --- a/xen/arch/x86/time.c Thu Aug 16 13:27:59 2007 +0100 +++ b/xen/arch/x86/time.c Thu Aug 30 12:08:29 2007 -0500 @@ -723,6 +723,41 @@ void update_domain_wallclock_time(struct spin_unlock(&wc_lock); } +/* calculate new tsc_scale factor based on ratio of new and old frequency + * and update time stamps to restart the period for the next calibration + */ +void do_change_freq(struct vcpu_time_info *info, unsigned int old, unsigned int new, int cpu_num) +{ + u64 new_mult, curr_tsc; + s8 new_shift; + struct cpu_time *...

...set, current_tick, cur_tsc; >> > + >> > + while (1) { >> > + sequence = READ_ONCE(tsc_pg->tsc_sequence); >> > + if (!sequence) >> > + break; >> > + >> > + scale = READ_ONCE(tsc_pg->tsc_scale); >> > + offset = READ_ONCE(tsc_pg->tsc_offset); >> > + rdtscll(cur_tsc); >> > + >> > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset; >> > + >> > + if (READ_ONCE(tsc_pg->tsc_sequence)...

...set, current_tick, cur_tsc; >> > + >> > + while (1) { >> > + sequence = READ_ONCE(tsc_pg->tsc_sequence); >> > + if (!sequence) >> > + break; >> > + >> > + scale = READ_ONCE(tsc_pg->tsc_scale); >> > + offset = READ_ONCE(tsc_pg->tsc_offset); >> > + rdtscll(cur_tsc); >> > + >> > + current_tick = mul_u64_u64_shr(cur_tsc, scale, 64) + offset; >> > + >> > + if (READ_ONCE(tsc_pg->tsc_sequence)...

...+ if (current_tick == U64_MAX) + rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); - if (tsc_pg->tsc_sequence != 0) { - /* - * Use the tsc page to compute the value. - */ - - while (1) { - u64 tmp; - u32 sequence = tsc_pg->tsc_sequence; - u64 cur_tsc; - u64 scale = tsc_pg->tsc_scale; - s64 offset = tsc_pg->tsc_offset; - - rdtscll(cur_tsc); - /* current_tick = ((cur_tsc *scale) >> 64) + offset */ - asm("mulq %3" - : "=d" (current_tick), "=a" (tmp) - : "a" (cur_tsc), "r" (scale)); - - current_tick += offs...

...ere reported there should be something. Actually, we already have an implementation of TSC page update in KVM (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does the following: 0) stash seq into seq_prev 1) seq = 0 making all reads from the page invalid 2) smp_wmb() 3) update tsc_scale, tsc_offset 4) smp_wmb() 5) set seq = seq_prev + 1 As far as I understand this helps with situations you described above as guest will notice either invalid value of 0 or seq change. In case the implementation in real Hyper-V is the same we're safe with compile barriers only. > > 3. You...

...ere reported there should be something. Actually, we already have an implementation of TSC page update in KVM (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does the following: 0) stash seq into seq_prev 1) seq = 0 making all reads from the page invalid 2) smp_wmb() 3) update tsc_scale, tsc_offset 4) smp_wmb() 5) set seq = seq_prev + 1 As far as I understand this helps with situations you described above as guest will notice either invalid value of 0 or seq change. In case the implementation in real Hyper-V is the same we're safe with compile barriers only. > > 3. You...

...ave an implementation of TSC page update in KVM >> (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does >> the following: >> >> 0) stash seq into seq_prev >> 1) seq = 0 making all reads from the page invalid >> 2) smp_wmb() >> 3) update tsc_scale, tsc_offset >> 4) smp_wmb() >> 5) set seq = seq_prev + 1 > > I hope they handle the case where seq_prev overflows and becomes 0 :) > >> As far as I understand this helps with situations you described above as >> guest will notice either invalid value of 0 or seq cha...

...ave an implementation of TSC page update in KVM >> (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does >> the following: >> >> 0) stash seq into seq_prev >> 1) seq = 0 making all reads from the page invalid >> 2) smp_wmb() >> 3) update tsc_scale, tsc_offset >> 4) smp_wmb() >> 5) set seq = seq_prev + 1 > > I hope they handle the case where seq_prev overflows and becomes 0 :) > >> As far as I understand this helps with situations you described above as >> guest will notice either invalid value of 0 or seq cha...

...id aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb arat cpb hw_pstate npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold bmi1 bogomips : 7023.90 TLB size : 1536 4K pages clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro six core AMD, above is one...

...page; > + u64 sequence, scale, offset, current_tick, cur_tsc; > + > + while (1) { > + sequence = READ_ONCE(tsc_pg->tsc_sequence); > + if (!sequence) > + break; > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + rdtscll(cur_tsc); > + > + current_tick = mul64x64_hi(cur_tsc, scale) + offset; > + > + if (READ_ONCE(tsc_pg->tsc_sequence) == sequence) > + retu...

...page; > + u64 sequence, scale, offset, current_tick, cur_tsc; > + > + while (1) { > + sequence = READ_ONCE(tsc_pg->tsc_sequence); > + if (!sequence) > + break; > + > + scale = READ_ONCE(tsc_pg->tsc_scale); > + offset = READ_ONCE(tsc_pg->tsc_offset); > + rdtscll(cur_tsc); > + > + current_tick = mul64x64_hi(cur_tsc, scale) + offset; > + > + if (READ_ONCE(tsc_pg->tsc_sequence) == sequence) > + retu...

Hi, merge window is about to close so I hope it's OK to make another try here. Changes since v2: - Add explicit READ_ONCE() to not rely on 'volatile' [Andy Lutomirski] - rdtsc() -> rdtsc_ordered() [Andy Lutomirski] - virt_rmb() -> smp_rmb() [Thomas Gleixner, Andy Lutomirski] Thomas, Andy, it seems the only blocker for the series was the ambiguity with TSC page read algorithm.

Hi, merge window is about to close so I hope it's OK to make another try here. Changes since v2: - Add explicit READ_ONCE() to not rely on 'volatile' [Andy Lutomirski] - rdtsc() -> rdtsc_ordered() [Andy Lutomirski] - virt_rmb() -> smp_rmb() [Thomas Gleixner, Andy Lutomirski] Thomas, Andy, it seems the only blocker for the series was the ambiguity with TSC page read algorithm.

...md_dcm aperfmperf pni pclmulqdq monitor ssse3 cx16 sse4_1 sse4_2 popcnt aes xsave avx lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 nodeid_msr topoext perfctr_core perfctr_nb cpb hw_pstate ssbd vmmcall arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold OS INFO on Debian 8： root at lkp-opteron1 /opt/rootfs/llvm_project/src/build# dpkg -l g++ cmake Desired=Unknown/Install/Remove/Purge/Hold | Status=Not/Inst/Conf-files/Unpacked/halF-conf/Half-inst/trig-aWait/Trig-pend |/ Err?=(none)/Rein...

...0000000 +0200 +++ 2009-07-10/xen/arch/x86/time.c 2009-07-15 09:59:20.000000000 +0200 @@ -1227,7 +1227,7 @@ int __init init_xen_time(void) if ( opt_consistent_tscs ) { int cpu; - for_each_cpu ( cpu ) + for_each_possible_cpu ( cpu ) per_cpu(cpu_time, cpu).tsc_scale = per_cpu(cpu_time, 0).tsc_scale; } --- 2009-07-10.orig/xen/common/perfc.c 2007-06-21 09:23:10.000000000 +0200 +++ 2009-07-10/xen/common/perfc.c 2009-07-15 10:03:02.000000000 +0200 @@ -136,13 +136,13 @@ void perfc_reset(unsigned char key) switch ( perfc_info[i].type ) {...