search for: trivialness

So I've got a Voicetronix card and it looks like the kernel driver works. Other than the 0's for ID info. vpb: Driver Version = 4.0 vpb: major = 251 vpb: tmp [0xfc8fec00] dev->res3 [0xfc8fec00] vpb: tmp [0xfc8c0000] dev->res2 [0xfc8c0000] vpb: 1WS Write cycle vpb: Manufactured 00/00/0000 vpb: Card version 00.00 vpb: Serial number 00000000 vpb: Setting up udev... vpb:1 V4PCI's

Hi, I have a general question on LoopUnswtich pass. Consider the following IR snippet: define i32 @test(i1 %cond) { br label %loop_begin loop_begin: br i1 %cond, label %loop_body, label %loop_exit loop_body: br label %do_something do_something: call void @some_func() noreturn nounwind br label %loop_begin loop_exit: ret i32 0 } declare void @some_func() noreturn After running

How does LLVM define "indirect call"? The documentation of CallSiteBase::getCalledFunction claims it returns null for indirect calls, but in practice it seems to return null for "non-trivial" calls. For example, it returns null for a direct call to a bitcast'ed function: %0 = call void bitcast (void (%struct.foo *)* @func to void (%struct.bar *)*)(%struct.bar *qux) By

Is there any written description of what "non trivialness" is there? On Sun, Apr 29, 2018, 2:49 PM Chandler Carruth via llvm-dev < llvm-dev at lists.llvm.org> wrote: > One of the last big missing pieces for the new PM is enabling non-trivial > loop unswitch at O3. > > The pass is now working well and passing all the testing I have...

I'm running into a problem with subregs during trivial coalescing in the linear scan allocator. Should RALinScan::attemptTrivialCoalescing be allowed to coalesce a COPY that uses a subreg as a destination? I've got the following sequence of code (unfortunately for an out of tree target) that is moving 32 and 64 bit sub-registers around within a 128 bit register. By the time the register

One of the last big missing pieces for the new PM is enabling non-trivial loop unswitch at O3. The pass is now working well and passing all the testing I have done as well as some others' testing (thanks Fedor!) so it should be ready to be enabled. I've done preliminary benchmarking on the test suite and SPEC and haven't seen any interesting regressions and quite a few improvements.

I have encountered a rather odd situation with Greedy where it will end up spilling a register that was populated with a zero (with a trivially rematerializable load-immediate instruction). In fact, it spills 3 such values (LICM moves stuff out of a loop, register coalescer replaces copies with load-immediates and then Greedy spills them). I personally can't think of a situation where a spill

I wanted to make sure that everyone was aware of a slight change we''ve made to the process for open source contributions. For *trivial* contributions, we are no longer requiring a Contributor License Agreement (CLA). Note that for most contributions a CLA signature is still required. I''m also working on making the overall CLA process easier, but that will take a little more time

Alright, go ahead with it. —Owen > On Nov 17, 2014, at 4:58 AM, Daniil Troshkov <troshkovdanil at gmail.com> wrote: > > Hi! > > I have not found test case. (It is because we have no target using "ExpandInsertToVectorThroughStack"). > But I tested it for target currently not included in llvm trunk. > > This fix correct and trivial, so I'm offering

I detected this bug using test case from platform which is not currently supported on llvm targets. (Our team is porting llvm on new target). Creating the test case will take some extra time. I'll try to do it ASAP. Have you any ideas about the test case? (targets using ExpandInsertToVectorThroughStack, etc...) On Wed, Nov 12, 2014 at 8:29 PM, Owen Anderson <resistor at mac.com> wrote:

On Mon, Oct 7, 2019 at 7:39 AM Jani Nikula <jani.nikula at linux.intel.com> wrote: > > On Fri, 04 Oct 2019, Krzysztof Kozlowski <krzk at kernel.org> wrote: > > drivers/gpu/drm/i915/Kconfig | 12 +- > > drivers/gpu/drm/i915/Kconfig.debug | 144 +++++++++++------------ > > Please split these out to a separate patch. Can't speak for others,

Hi, This is a very trivial question, and I do not know why I cannot remember the answer at all! How does one get the entire system information (which OS, R version....etc) using an R command? Thanks, Kevin ------------------------------------------------------------------------------ Ko-Kang Kevin Wang Postgraduate PGDipSci Student Department of Statistics University of Auckland New Zealand

Hi; I'm new to Dovecot and Postfix. I'm trying to enable these with MySQL support and postfixadmin. I've got all those services up and running (finally!); however, I can't figure out if the emails are being received and/or stored. I'm pretty sure Postfix is receiving them because I dealt with certain errors and they're now gone. Here's some data: Dovecot ver. 0.91

Hi, I’m looking at some patterns which failed to import, and when I reduced them I was surprised to find a variety of complicated patterns successfully import, but the most trivial patterns I can come up with fail. If I add this pattern to test/TableGen/GlobalISelEmitter.td: def : Pat < (mul i32:$y, i32:$x), (MUL $x, $y) >; test/TableGen/GlobalISelEmitter.td:1196:1: warning: Skipped

Nicolas Geoffray wrote: > Hi Andrew, > > Andrew Haley wrote: >> Also, if you can make the capability generic enough to use in Shark >> (more at http://gbenson.net/) that would be very useful. > > Agree. > >> The key, I suspect, is to allow the Java front end mark an array.length >> field in such a way that LLVM knows that field doesn't alias

Hi Owen! The "First store the whole vector" is without uses and will be deleted later. I've attached trivial patch to fix it. I have no commit access so if patch is OK, please, commit it . Danil. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141112/52592eeb/attachment.html>

On Mon, 07 Oct 2019, Krzysztof Kozlowski <krzk at kernel.org> wrote: > On Mon, 7 Oct 2019 at 18:09, Alex Deucher <alexdeucher at gmail.com> wrote: >> >> On Mon, Oct 7, 2019 at 7:39 AM Jani Nikula <jani.nikula at linux.intel.com> wrote: >> > >> > On Fri, 04 Oct 2019, Krzysztof Kozlowski <krzk at kernel.org> wrote: >> > >

That's an unintentional change. However, the reason for this change was to make optional of trivially copyable types trivially copyable, adding a user-provided move ctor would break that again :( I'm leaning towards making the non-trivial version of llvm::Optional more like std::optional. In the long term std::optional is going to replace llvm::Optional. How bad would that be for your use

The immediate change I have in mind is in CallGraph; our implementation of LowerCall in AMDGPU currently relies on the the callee arguments being lowered before the call is lowered, and we simply do not support indirect calls. However, we should be able to support these bitcast calls, as they are effectively direct for our purposes, but the CallGraph does not seem to consider them (it uses

On Wed, Jan 24, 2018 at 11:47 PM, Benjamin Kramer <benny.kra at gmail.com> wrote: > That's an unintentional change. However, the reason for this change > was to make optional of trivially copyable types trivially copyable, > adding a user-provided move ctor would break that again :( > > I'm leaning towards making the non-trivial version of llvm::Optional > more