search for: transport_triggered_architectures

Hello LLVM people, Our customizable TTA target [1] is capable of having plenty of registers and register file ports to improve instruction level parallelism and reduce spills. It's totally up to the designer of the particular TTA processor how much the processor has registers and register file resources along with other TTA components. We have ported LLVM 2.1 to produce an intermediate TTA

We are going to use LLVM in a compiler project for transport triggered processors. See Wikipedia for more on transport triggering: <http://en.wikipedia.org/wiki/Transport_Triggered_Architectures>. One thing we need is some sort of libc. We are targeting embedded systems, and I have been looking at things like newlib. Are there people out there doing something similar? Or any advice or opinions as to how go about the whole thing? -- Pertti

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

This is in response to Reid's and John's comments about intrinsics. The setting of the work is a project on reconfigurable processors using the Transport Triggered Architecture (TTA) <http://en.wikipedia.org/wiki/Transport_triggered_architecture>. For the compiler this means that the target architecture is not fixed, but rather an instance of a processor template. Different

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

Pertti Kellomäki wrote: > This is in response to Reid's and John's comments about > intrinsics. > > The setting of the work is a project on reconfigurable > processors using the Transport Triggered Architecture (TTA) > <http://en.wikipedia.org/wiki/Transport_triggered_architecture>. > For the compiler this means that the target architecture > is not fixed, but

Hi Pertti, On Thu, 2006-11-09 at 15:29 +0200, Pertti Kellomäki wrote: > I managed to compile newlib with llvm-gcc yesterday. That > is, the machine independent part is now basically done, and > the syscall part contains no-op stubs provided by libgloss. > I haven't tested the port yet, but since newlib has already > been ported to many architectures, I would be pretty surprised

I managed to compile newlib with llvm-gcc yesterday. That is, the machine independent part is now basically done, and the syscall part contains no-op stubs provided by libgloss. I haven't tested the port yet, but since newlib has already been ported to many architectures, I would be pretty surprised if there were any major problems. A couple of things I noticed when configuring newlib for