Displaying 6 results from an estimated 6 matches for "tpr_threshold".
2012 Dec 18
0
[PATCH] nested vmx: nested TPR shadow/threshold emulation
...,7 +324,9 @@ void vmx_intr_assist(void)
}
out:
- if ( !cpu_has_vmx_virtual_intr_delivery && cpu_has_vmx_tpr_shadow )
+ if ( !nestedhvm_vcpu_in_guestmode(v) &&
+ !cpu_has_vmx_virtual_intr_delivery &&
+ cpu_has_vmx_tpr_shadow )
__vmwrite(TPR_THRESHOLD, tpr_threshold);
}
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index b005816..7b27d2d 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -471,8 +471,7 @@ void nvmx_update_exec_control(struct vcpu *v, u32 host_cntrl)
shadow_cntrl = __n2_e...
2006 Dec 01
0
[PATCH] A fix for CR8 acceleration on 64bit guest
This patch is a small fix for CR8 acceleration on 64bit guest.
For current CR8 acceleration, we do not call update_tpr_threshold() at
every VMEXIT.
But at some situations, we cannot inject guest interrupts in time. And
at some critical time, it will bring up a blue screen to 64bit Windows
guest.
Try this scenario:
1) At one VMIT, tpr = TPR_THRESHOLD, but tpr < pending IRQ, and we
cannot inject it to guest bec...
2012 Sep 14
0
[ PATCH v3 2/3] xen: enable Virtual-interrupt delivery
...r_irr(vector, vlapic);
diff -r 7c6844dd4a0d xen/arch/x86/hvm/vmx/intr.c
--- a/xen/arch/x86/hvm/vmx/intr.c Tue Sep 11 15:34:36 2012 +0800
+++ b/xen/arch/x86/hvm/vmx/intr.c Fri Sep 14 09:16:35 2012 +0800
@@ -206,6 +206,7 @@ void vmx_intr_assist(void)
struct vcpu *v = current;
unsigned int tpr_threshold = 0;
enum hvm_intblk intblk;
+ int pt_vector = -1;
/* Block event injection when single step with MTF. */
if ( unlikely(v->arch.hvm_vcpu.single_step) )
@@ -216,7 +217,7 @@ void vmx_intr_assist(void)
}
/* Crank the handle on interrupt state. */
- pt_update_irq(v...
2006 Oct 24
1
RE: [Patch] Add hardware CR8 acceleration for TPRaccessing
...ts.xensource.com
>> Subject: RE: [Xen-devel] [Patch] Add hardware CR8
>> acceleration for TPR accessing
>>
>> Hi, Travis,
>> Is there anything in SVM similar to TPP-threshold in VMX?
>> If no, I really need to find a better place for the
>> vlapic_update_tpr_threshold().
>
>I don''t think that''s the question/statement: any code in hvm
>directory should be guaranteed to be callable by both Intel
>and AMD code. The code you''ve just added makes direct use of
>the vmwrite instruction, which there isn''t a correspon...
2009 Jul 07
0
[PATCH] [VMX] Add support for Pause-Loop Exiting
...D_GUEST)
+#define cpu_has_vmx_ple \
+ (vmx_secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
/* GUEST_INTERRUPTIBILITY_INFO flags. */
#define VMX_INTR_SHADOW_STI 0x00000001
@@ -279,6 +282,8 @@ enum vmcs_field {
VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
TPR_THRESHOLD = 0x0000401c,
SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
+ PLE_GAP = 0x00004020,
+ PLE_WINDOW = 0x00004022,
VM_INSTRUCTION_ERROR = 0x00004400,
VM_EXIT_REASON = 0x00004402,
VM_EXIT...
2013 Jan 07
9
[PATCH v2 0/3] nested vmx bug fixes
Changes from v1 to v2:
- Use a macro to replace the hardcode in patch 1/3.
This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area
synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH,
and CR0/CR4 emulation.
Please help to review and pull.
Thanks,
Dongxiao
Dongxiao Xu (3):
nested vmx: emulate IA32_VMX_MISC MSR
nested vmx: synchronize page