search for: tmp18

Displaying 20 results from an estimated 36 matches for "tmp18".

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2007 Jul 03
1
[LLVMdev] Question about Constant Expressions
Hi! Is there a pass that will remove constant expressions from appearing within other expressions? For instance it would convert the call: %tmp20 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp18 ) ; <i32> [#uses=0] Into: %tmpFresh = getelementptr [4 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses = 1] %tmp20 = tail call i32 (i8*, ...)* @printf( i8* %tmpFresh, i32 %tmp18 ) ; <i32> [#uses=0] (Ideally it would do this as an .s -> .s transformation and be accessible th...
2008 Feb 16
0
[LLVMdev] linux/x86-64 codegen support
libcpp/charset.c:631 turns into: %tmp16 = tail call i64 @strlen( i8* %to ) nounwind readonly ; <i64> [#uses=1] %tmp18 = tail call i64 @strlen( i8* %from ) nounwind readonly ; <i64> [#uses=1] %tmp19 = add i64 %tmp16, 2 ; <i64> [#uses=1] %tmp20 = add i64 %tmp19, %tmp18 ; <i64> [#uses=1] %tmp21 = tail call i8* @alloca( i64 %tmp20 ) nounwind ; &l...
2008 Feb 16
2
[LLVMdev] linux/x86-64 codegen support
PR1711 is an x86 codegen problem that is blocking adoption of llvm-gcc by people using linux on x86-64 boxes. Could someone with access to one of these boxes take a look? I'll help try to debug this, but I don't have access to a machine. I bet it's a small tweak required in the x86 backend. Thanks! -Chris
2007 Nov 15
0
[LLVMdev] BasicAliasAnalysis and out-of-bound GEP indices
...o %struct.ehci_hcd* ; later in the source, a pointer to the parent struct is obtained ; from %tmp910 using inner field's offset knowledge ; (__builtin_offsetof operator in the C source) %tmp1415 = bitcast %struct.ehci_hcd* %tmp910 to [0 x i32]* %tmp1617 = bitcast [0 x i32]* %tmp1415 to i8* %tmp18 = getelementptr i8* %tmp1617, i32 -4 %tmp1819 = bitcast i8* %tmp18 to %struct.usb_hcd* -= after instcombine =- %tmp18 = getelementptr %struct.usb_hcd* %hcd, i32 0, i32 1, i32 -1 %tmp1819 = bitcast i32* %tmp18 to %struct.usb_hcd* It is an example of GEP instruction that, on purpose, crosses the b...
2011 Oct 06
2
[LLVMdev] A potential bug
...(i32* %tv_usec) // intrinsic function call ... 16. %tmp16 = load i32* %tv_usec.safe_r, align 4, !tbaa !4 17. %tv_sec17 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, i32 0 18. %tv_sec17.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_sec17) // intrinsic function call ... 19. %tmp18 = load i32* %tv_sec17.safe_r, align 4, !tbaa !4 20. %tv_usec19 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, i32 1 21. %tv_usec19.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_usec19) // intrinsic function call 22. %tmp20 = load i32* %tv_usec19.safe_r, align 4, !tbaa !4 23....
2010 Sep 10
1
[LLVMdev] Missing Optimization Opportunities
...%tmp15 = and i1 %tmp13, %tmp14 ; <i1> [#uses=1] tail call void @spa.assert(i1 %tmp15) %tmp16 = and i1 %tmp8, %tmp10 ; <i1> [#uses=1] %tmp17 = and i1 %tmp13, %tmp16 ; <i1> [#uses=1] tail call void @spa.assert(i1 %tmp17) %tmp18 = and i1 %tmp13, %tmp7 ; <i1> [#uses=1] tail call void @spa.assert(i1 %tmp18) ret void } Please notice the following code sequences are not optimal: %tmp5 = and i1 %tmp2, %tmp4 ; <i1> [#uses=1] %tmp14 = and i1 %tmp2, %tmp5 ;...
2007 Jun 12
3
[LLVMdev] ARM backend problem ?
...ore i32 1, i32* %f store i32 1, i32* %i store i32 0 , i32* %zero store i32 1 , i32* %inc %tmp7 = load i32* %n %tmp8 = load i32* %zero %tmp6 = icmp sgt i32 %tmp7, %tmp8 br i1 %tmp6, label %then4, label %else12 then4: %tmp14 = load i32* %i %tmp16 = load i32* %n %tmp18 = load i32* %inc %tmp15 = add i32 %tmp16, %tmp18 %tmp13 = icmp slt i32 %tmp14, %tmp15 br i1 %tmp13, label %then11, label %else12 then11: %tmp20 = load i32* %f %tmp22 = alloca i32 store i32 1 , i32* %tmp22 %tmp23 = load i32* %tmp22 %tmp24 = load i32* %i %tmp21 = add i3...
2011 Oct 06
2
[LLVMdev] A potential bug
...t; 16.  %tmp16 = load i32* %tv_usec.safe_r, align 4, !tbaa !4 >> 17.  %tv_sec17 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, >> i32 0 >> 18.  %tv_sec17.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_sec17)  // >> intrinsic function call ... >> 19.  %tmp18 = load i32* %tv_sec17.safe_r, align 4, !tbaa !4 >> 20.  %tv_usec19 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, >> i32 1 >> 21.  %tv_usec19.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_usec19) >> // intrinsic function call >> 22.  %tmp20 = load i3...
2007 Nov 15
3
[LLVMdev] BasicAliasAnalysis and out-of-bound GEP indices
On 11/15/07, Duncan Sands <baldrick at free.fr> wrote: > Hi, > > > Sadly, this will break a very common idiom. In GCC, we discovered it > > to be common enough that it broke a *bunch* of C code. > > > > In particular, you will break > > > > struct foo { > > int a; > > char name[0]; > > } > > > > bar = malloc(sizeof
2011 Oct 06
0
[LLVMdev] A potential bug
...function call ... > 16.  %tmp16 = load i32* %tv_usec.safe_r, align 4, !tbaa !4 > 17.  %tv_sec17 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, > i32 0 > 18.  %tv_sec17.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_sec17)  // > intrinsic function call ... > 19.  %tmp18 = load i32* %tv_sec17.safe_r, align 4, !tbaa !4 > 20.  %tv_usec19 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 0, > i32 1 > 21.  %tv_usec19.safe_r = call i32* @llvm.guard.load.p0i32(i32* %tv_usec19) > // intrinsic function call > 22.  %tmp20 = load i32* %tv_usec19.safe_r...
2007 Jun 12
0
[LLVMdev] ARM backend problem ?
...1 , i32* %inc > > > > %tmp7 = load i32* %n > > %tmp8 = load i32* %zero > > %tmp6 = icmp sgt i32 %tmp7, %tmp8 > > br i1 %tmp6, label %then4, label %else12 > > > > then4: > > %tmp14 = load i32* %i > > %tmp16 = load i32* %n > > %tmp18 = load i32* %inc > > %tmp15 = add i32 %tmp16, %tmp18 > > %tmp13 = icmp slt i32 %tmp14, %tmp15 > > br i1 %tmp13, label %then11, label %else12 > > > > then11: > > %tmp20 = load i32* %f > > %tmp22 = alloca i32 > > store i32 1 , i32* %tmp22 &g...
2010 Nov 23
1
[LLVMdev] Unrolling loops into constant-time expressions
..., label %3 bb.nph: ; preds = %0 %tmp4 = add i32 %x, -1 %tmp6 = add i32 %x, -2 %tmp16 = add i32 %x, -3 %tmp7 = zext i32 %tmp6 to i33 %tmp5 = zext i32 %tmp4 to i33 %tmp17 = zext i32 %tmp16 to i33 %tmp15 = mul i33 %tmp5, %tmp7 %tmp18 = mul i33 %tmp15, %tmp17 %tmp8 = mul i32 %tmp4, %tmp6 %tmp19 = lshr i33 %tmp18, 1 %2 = shl i32 %tmp8, 2 %tmp20 = trunc i33 %tmp19 to i32 %tmp12 = mul i32 %x, 5 %tmp1125 = and i32 %2, -8 %tmp21 = mul i32 %tmp20, 1431655764 %tmp13 = add i32 %tmp1125, %tmp12 %tmp14...
2011 Oct 06
0
[LLVMdev] A potential bug
....safe_r, align 4, !tbaa !4 > >> 17. %tv_sec17 = getelementptr inbounds %struct.timeval* %agg.tmp12, i32 > 0, > >> i32 0 > >> 18. %tv_sec17.safe_r = call i32* @llvm.guard.load.p0i32(i32* > %tv_sec17) // > >> intrinsic function call ... > >> 19. %tmp18 = load i32* %tv_sec17.safe_r, align 4, !tbaa !4 > >> 20. %tv_usec19 = getelementptr inbounds %struct.timeval* %agg.tmp12, > i32 0, > >> i32 1 > >> 21. %tv_usec19.safe_r = call i32* @llvm.guard.load.p0i32(i32* > %tv_usec19) > >> // intrinsic function call...
2010 Jan 29
2
[LLVMdev] 64bit MRV problem: { float, float, float} -> { double, float }
...ses=1] %1 = fadd float %aY, 5.000000e-01 ; <float> [#uses=1] %2 = fadd float %aX, 5.000000e-01 ; <float> [#uses=1] %tmp16.i.i = bitcast float %1 to i32 ; <i32> [#uses=1] %tmp17.i.i = zext i32 %tmp16.i.i to i96 ; <i96> [#uses=1] %tmp18.i.i = shl i96 %tmp17.i.i, 32 ; <i96> [#uses=1] %tmp19.i = zext i96 %tmp18.i.i to i128 ; <i128> [#uses=1] %tmp8.i = lshr i128 %tmp19.i, 32 ; <i128> [#uses=1] %tmp9.i = trunc i128 %tmp8.i to i32 ; <i32> [#uses=1] %tmp10.i...
2008 Sep 30
0
[LLVMdev] Generalizing shuffle vector
...M, Mon Ping Wang <wangmp at apple.com> wrote: > The problem with generating insert and extracts is that we can generate poor > code > %tmp16 = extractelement <4 x float> %f4b, i32 0 > %f8a = insertelement <8 x float> %f8a, float %tmp16, i32 0 > %tmp18 = extractelement <4 x float> %f4b, i32 1 > %f8c = insertelement <8 x float> %f8b, float %tmp18, i32 1 > ... > For X86, legalize will convert each insertelement to become a vector > shuffle. We are very careful in combining vector shuffles because we don't &...
2011 Oct 06
1
[LLVMdev] A potential bug
...7.  %tv_sec17 = getelementptr inbounds %struct.timeval* %agg.tmp12, >> >> i32 0, >> >> i32 0 >> >> 18.  %tv_sec17.safe_r = call i32* @llvm.guard.load.p0i32(i32* >> >> %tv_sec17)  // >> >> intrinsic function call ... >> >> 19.  %tmp18 = load i32* %tv_sec17.safe_r, align 4, !tbaa !4 >> >> 20.  %tv_usec19 = getelementptr inbounds %struct.timeval* %agg.tmp12, >> >> i32 0, >> >> i32 1 >> >> 21.  %tv_usec19.safe_r = call i32* @llvm.guard.load.p0i32(i32* >> >> %tv_usec19) &gt...
2008 Sep 30
4
[LLVMdev] Generalizing shuffle vector
...f4b, <4xf32>%f4c, <8xi32> <0, 1, 2, 3, 4, 5, 6, 7> The problem with generating insert and extracts is that we can generate poor code %tmp16 = extractelement <4 x float> %f4b, i32 0 %f8a = insertelement <8 x float> %f8a, float %tmp16, i32 0 %tmp18 = extractelement <4 x float> %f4b, i32 1 %f8c = insertelement <8 x float> %f8b, float %tmp18, i32 1 ... For X86, legalize will convert each insertelement to become a vector shuffle. We are very careful in combining vector shuffles because we don't want to produce...
2010 Nov 07
0
[LLVMdev] Hoisting elements of array argument into registers
...; preds = %entry %.promoted1.i = load i32* %1, align 4 %tmp12.i = add i32 %a, -1 %tmp13.i = zext i32 %tmp12.i to i33 %tmp14.i = add i32 %a, -2 %tmp15.i = zext i32 %tmp14.i to i33 %tmp16.i = mul i33 %tmp13.i, %tmp15.i %tmp17.i = lshr i33 %tmp16.i, 1 %tmp18.i = trunc i33 %tmp17.i to i32 %tmp20.i = mul i32 %.promoted1.i, 5 %tmp21.i = add i32 %tmp20.i, -5 %tmp22.i = mul i32 %tmp21.i, %tmp12.i %tmp9.i = mul i32 %a, %a %.promoted2.i = load i32* %2, align 4 %tmp25.i = mul i32 %tmp18.i, 5 %tmp.i = sub i32 %.promoted1.i, %a %tmp10.i = add i32...
2008 Feb 10
2
[LLVMdev] Instrumenting virtual function calls
...d %"struct.Q::Function"** %tmp9.i, align 4 ; < %"struct.Q::Function"*> [#uses=2] %tmp17.i = getelementptr %"struct.Q::BinaryOperation<bool,bool,bool,Q::AddOperator>"* %this, i32 0, i32 1, i32 0 ; <%"struct.Q::Function"**> [#uses=1] %tmp18.i = load %"struct.Q::Function"** %tmp17.i, align 4 ; < %"struct.Q::Function"*> [#uses=2] %tmp33.i = getelementptr %"struct.Q::Function"* %tmp18.i, i32 0, i32 0, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=1] %tmp34.i = load i32 (...)*** %tmp33.i, ali...
2008 Jan 12
1
[LLVMdev] Labels
...ll( ) %tmp6 = icmp eq i32 %tmp5, 0 br i1 %tmp6, label %UnifiedReturnBlock, label %cond_next11 cond_next11: %tmp12 = load i8** @yybuf, align 4 %tmp13 = load i32* @yypos, align 4 %tmp14 = getelementptr i8* %tmp12, i32 %tmp13 %tmp15 = load i8* %tmp14, align 1 %tmp1516 = sext i8 %tmp15 to i32 %tmp18 = icmp eq i32 %tmp1516, %c br i1 %tmp18, label %cond_true21, label %UnifiedReturnBlock cond_true21: %tmp23 = add i32 %tmp13, 1 store i32 %tmp23, i32* @yypos, align 4 ret i32 1 UnifiedReturnBlock: ret i32 0 } define i32 @yymatchString(i8* %s) { entry: %tmp1 = load i32* @yypos, align 4 %tmp...